//                                                                             
// File:       ./headers/mac_hwsch_reg.h                                       
// Creator:    afang                                                           
// Time:       Friday Oct 5, 2012 [2:06:17 pm]                                 
//                                                                             
// Path:       /trees/afang/afang-dev/work/blueprint/project/beeliner/releases/AutogenVersion/rdl
// Arguments:  /cad/denali/blueprint/3.7.4//Linux-64bit/blueprint -odir        
//             ./headers -codegen ath_ch.codegen -ath_ch -Wdesc                
//             mac_hwsch_reg.rdl                                               
//                                                                             
// Sources:    /trees/afang/afang-dev/work/blueprint/project/beeliner/releases/AutogenVersion/rdl/mac_hwsch_reg.rdl
//             /trees/afang/afang-dev/work/blueprint/project/beeliner/releases/AutogenVersion/rdl/ath_ch.pm
//                                                                             
// Blueprint:   3.7.4 (Fri Jan 9 05:41:17 PST 2009)                            
// Machine:    crimson                                                         
// OS:         Linux 2.6.9-103.ELsmp                                           
// Description:                                                                
//                                                                             
// No Description Provided                                                     
//                                                                             
//                                                                             


#ifndef _MAC_HWSCH_REG_H_
#define _MAC_HWSCH_REG_H_

// 0x0000 (HWSCH_DIFS_LIMIT_1_0)
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_1_MSB                          31
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_1_LSB                          26
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_1_MASK                         0xfc000000
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_1_GET(x)                       (((x) & HWSCH_DIFS_LIMIT_1_0_RESERVED_1_MASK) >> HWSCH_DIFS_LIMIT_1_0_RESERVED_1_LSB)
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_1_SET(x)                       (((0x0 | (x)) << HWSCH_DIFS_LIMIT_1_0_RESERVED_1_LSB) & HWSCH_DIFS_LIMIT_1_0_RESERVED_1_MASK)
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_1_RESET                        0
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_1_MSB                 25
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_1_LSB                 16
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_1_MASK                0x03ff0000
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_1_GET(x)              (((x) & HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_1_MASK) >> HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_1_LSB)
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_1_SET(x)              (((0x0 | (x)) << HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_1_LSB) & HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_1_MASK)
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_1_RESET               28
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_0_MSB                          15
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_0_LSB                          10
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_0_MASK                         0x0000fc00
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_0_GET(x)                       (((x) & HWSCH_DIFS_LIMIT_1_0_RESERVED_0_MASK) >> HWSCH_DIFS_LIMIT_1_0_RESERVED_0_LSB)
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_0_SET(x)                       (((0x0 | (x)) << HWSCH_DIFS_LIMIT_1_0_RESERVED_0_LSB) & HWSCH_DIFS_LIMIT_1_0_RESERVED_0_MASK)
#define HWSCH_DIFS_LIMIT_1_0_RESERVED_0_RESET                        0
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_0_MSB                 9
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_0_LSB                 0
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_0_MASK                0x000003ff
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_0_GET(x)              (((x) & HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_0_MASK) >> HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_0_LSB)
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_0_SET(x)              (((0x0 | (x)) << HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_0_LSB) & HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_0_MASK)
#define HWSCH_DIFS_LIMIT_1_0_SW_MTU_DIFS_LIMIT_0_RESET               37
#define HWSCH_DIFS_LIMIT_1_0_ADDRESS                                 0x000000
#define HWSCH_DIFS_LIMIT_1_0_HW_MASK                                 0xffffffff
#define HWSCH_DIFS_LIMIT_1_0_SW_MASK                                 0xffffffff
#define HWSCH_DIFS_LIMIT_1_0_RSTMASK                                 0x03ff03ff
#define HWSCH_DIFS_LIMIT_1_0_RESET                                   0x001c0025

// 0x0004 (HWSCH_DIFS_LIMIT_3_2)
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_1_MSB                          31
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_1_LSB                          26
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_1_MASK                         0xfc000000
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_1_GET(x)                       (((x) & HWSCH_DIFS_LIMIT_3_2_RESERVED_1_MASK) >> HWSCH_DIFS_LIMIT_3_2_RESERVED_1_LSB)
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_1_SET(x)                       (((0x0 | (x)) << HWSCH_DIFS_LIMIT_3_2_RESERVED_1_LSB) & HWSCH_DIFS_LIMIT_3_2_RESERVED_1_MASK)
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_1_RESET                        0
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_3_MSB                 25
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_3_LSB                 16
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_3_MASK                0x03ff0000
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_3_GET(x)              (((x) & HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_3_MASK) >> HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_3_LSB)
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_3_SET(x)              (((0x0 | (x)) << HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_3_LSB) & HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_3_MASK)
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_3_RESET               28
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_0_MSB                          15
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_0_LSB                          10
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_0_MASK                         0x0000fc00
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_0_GET(x)                       (((x) & HWSCH_DIFS_LIMIT_3_2_RESERVED_0_MASK) >> HWSCH_DIFS_LIMIT_3_2_RESERVED_0_LSB)
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_0_SET(x)                       (((0x0 | (x)) << HWSCH_DIFS_LIMIT_3_2_RESERVED_0_LSB) & HWSCH_DIFS_LIMIT_3_2_RESERVED_0_MASK)
#define HWSCH_DIFS_LIMIT_3_2_RESERVED_0_RESET                        0
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_2_MSB                 9
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_2_LSB                 0
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_2_MASK                0x000003ff
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_2_GET(x)              (((x) & HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_2_MASK) >> HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_2_LSB)
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_2_SET(x)              (((0x0 | (x)) << HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_2_LSB) & HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_2_MASK)
#define HWSCH_DIFS_LIMIT_3_2_SW_MTU_DIFS_LIMIT_2_RESET               37
#define HWSCH_DIFS_LIMIT_3_2_ADDRESS                                 0x000004
#define HWSCH_DIFS_LIMIT_3_2_HW_MASK                                 0xffffffff
#define HWSCH_DIFS_LIMIT_3_2_SW_MASK                                 0xffffffff
#define HWSCH_DIFS_LIMIT_3_2_RSTMASK                                 0x03ff03ff
#define HWSCH_DIFS_LIMIT_3_2_RESET                                   0x001c0025

// 0x0008 (HWSCH_DIFS_LIMIT_5_4)
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_1_MSB                          31
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_1_LSB                          26
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_1_MASK                         0xfc000000
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_1_GET(x)                       (((x) & HWSCH_DIFS_LIMIT_5_4_RESERVED_1_MASK) >> HWSCH_DIFS_LIMIT_5_4_RESERVED_1_LSB)
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_1_SET(x)                       (((0x0 | (x)) << HWSCH_DIFS_LIMIT_5_4_RESERVED_1_LSB) & HWSCH_DIFS_LIMIT_5_4_RESERVED_1_MASK)
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_1_RESET                        0
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_5_MSB                 25
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_5_LSB                 16
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_5_MASK                0x03ff0000
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_5_GET(x)              (((x) & HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_5_MASK) >> HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_5_LSB)
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_5_SET(x)              (((0x0 | (x)) << HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_5_LSB) & HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_5_MASK)
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_5_RESET               28
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_0_MSB                          15
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_0_LSB                          10
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_0_MASK                         0x0000fc00
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_0_GET(x)                       (((x) & HWSCH_DIFS_LIMIT_5_4_RESERVED_0_MASK) >> HWSCH_DIFS_LIMIT_5_4_RESERVED_0_LSB)
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_0_SET(x)                       (((0x0 | (x)) << HWSCH_DIFS_LIMIT_5_4_RESERVED_0_LSB) & HWSCH_DIFS_LIMIT_5_4_RESERVED_0_MASK)
#define HWSCH_DIFS_LIMIT_5_4_RESERVED_0_RESET                        0
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_4_MSB                 9
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_4_LSB                 0
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_4_MASK                0x000003ff
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_4_GET(x)              (((x) & HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_4_MASK) >> HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_4_LSB)
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_4_SET(x)              (((0x0 | (x)) << HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_4_LSB) & HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_4_MASK)
#define HWSCH_DIFS_LIMIT_5_4_SW_MTU_DIFS_LIMIT_4_RESET               37
#define HWSCH_DIFS_LIMIT_5_4_ADDRESS                                 0x000008
#define HWSCH_DIFS_LIMIT_5_4_HW_MASK                                 0xffffffff
#define HWSCH_DIFS_LIMIT_5_4_SW_MASK                                 0xffffffff
#define HWSCH_DIFS_LIMIT_5_4_RSTMASK                                 0x03ff03ff
#define HWSCH_DIFS_LIMIT_5_4_RESET                                   0x001c0025

// 0x000c (HWSCH_DIFS_LIMIT_7_6)
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_1_MSB                          31
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_1_LSB                          26
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_1_MASK                         0xfc000000
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_1_GET(x)                       (((x) & HWSCH_DIFS_LIMIT_7_6_RESERVED_1_MASK) >> HWSCH_DIFS_LIMIT_7_6_RESERVED_1_LSB)
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_1_SET(x)                       (((0x0 | (x)) << HWSCH_DIFS_LIMIT_7_6_RESERVED_1_LSB) & HWSCH_DIFS_LIMIT_7_6_RESERVED_1_MASK)
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_1_RESET                        0
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_7_MSB                 25
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_7_LSB                 16
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_7_MASK                0x03ff0000
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_7_GET(x)              (((x) & HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_7_MASK) >> HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_7_LSB)
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_7_SET(x)              (((0x0 | (x)) << HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_7_LSB) & HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_7_MASK)
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_7_RESET               28
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_0_MSB                          15
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_0_LSB                          10
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_0_MASK                         0x0000fc00
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_0_GET(x)                       (((x) & HWSCH_DIFS_LIMIT_7_6_RESERVED_0_MASK) >> HWSCH_DIFS_LIMIT_7_6_RESERVED_0_LSB)
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_0_SET(x)                       (((0x0 | (x)) << HWSCH_DIFS_LIMIT_7_6_RESERVED_0_LSB) & HWSCH_DIFS_LIMIT_7_6_RESERVED_0_MASK)
#define HWSCH_DIFS_LIMIT_7_6_RESERVED_0_RESET                        0
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_6_MSB                 9
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_6_LSB                 0
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_6_MASK                0x000003ff
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_6_GET(x)              (((x) & HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_6_MASK) >> HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_6_LSB)
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_6_SET(x)              (((0x0 | (x)) << HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_6_LSB) & HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_6_MASK)
#define HWSCH_DIFS_LIMIT_7_6_SW_MTU_DIFS_LIMIT_6_RESET               37
#define HWSCH_DIFS_LIMIT_7_6_ADDRESS                                 0x00000c
#define HWSCH_DIFS_LIMIT_7_6_HW_MASK                                 0xffffffff
#define HWSCH_DIFS_LIMIT_7_6_SW_MASK                                 0xffffffff
#define HWSCH_DIFS_LIMIT_7_6_RSTMASK                                 0x03ff03ff
#define HWSCH_DIFS_LIMIT_7_6_RESET                                   0x001c0025

// 0x0010 (HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RESERVED_0_MSB                31
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RESERVED_0_LSB                17
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RESERVED_0_MASK               0xfffe0000
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RESERVED_0_GET(x)             (((x) & HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RESERVED_0_MASK) >> HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RESERVED_0_LSB)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RESERVED_0_SET(x)             (((0x0 | (x)) << HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RESERVED_0_LSB) & HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RESERVED_0_MASK)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RESERVED_0_RESET              0
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_PIFS_LIMIT_MSB             16
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_PIFS_LIMIT_LSB             8
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_PIFS_LIMIT_MASK            0x0001ff00
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_PIFS_LIMIT_GET(x)          (((x) & HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_PIFS_LIMIT_MASK) >> HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_PIFS_LIMIT_LSB)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_PIFS_LIMIT_SET(x)          (((0x0 | (x)) << HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_PIFS_LIMIT_LSB) & HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_PIFS_LIMIT_MASK)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_PIFS_LIMIT_RESET           19
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_MTU_SLOT_LIMIT_MSB         7
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_MTU_SLOT_LIMIT_LSB         0
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_MTU_SLOT_LIMIT_MASK        0x000000ff
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_MTU_SLOT_LIMIT_GET(x)      (((x) & HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_MTU_SLOT_LIMIT_MASK) >> HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_MTU_SLOT_LIMIT_LSB)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_MTU_SLOT_LIMIT_SET(x)      (((0x0 | (x)) << HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_MTU_SLOT_LIMIT_LSB) & HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_MTU_SLOT_LIMIT_MASK)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_MTU_SLOT_LIMIT_RESET       9
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_ADDRESS                       0x000010
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_HW_MASK                       0xffffffff
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_SW_MASK                       0xffffffff
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RSTMASK                       0x0001ffff
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_RESET                         0x00001309

// 0x0014 (HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RESERVED_0_MSB              31
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RESERVED_0_LSB              16
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RESERVED_0_MASK             0xffff0000
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RESERVED_0_GET(x)           (((x) & HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RESERVED_0_MASK) >> HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RESERVED_0_LSB)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RESERVED_0_SET(x)           (((0x0 | (x)) << HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RESERVED_0_LSB) & HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RESERVED_0_MASK)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RESERVED_0_RESET            0
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_SW_MTU_EIFS_LIMIT_MSB       15
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_SW_MTU_EIFS_LIMIT_LSB       0
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_SW_MTU_EIFS_LIMIT_MASK      0x0000ffff
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_SW_MTU_EIFS_LIMIT_GET(x)    (((x) & HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_SW_MTU_EIFS_LIMIT_MASK) >> HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_SW_MTU_EIFS_LIMIT_LSB)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_SW_MTU_EIFS_LIMIT_SET(x)    (((0x0 | (x)) << HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_SW_MTU_EIFS_LIMIT_LSB) & HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_SW_MTU_EIFS_LIMIT_MASK)
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_SW_MTU_EIFS_LIMIT_RESET     90
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_ADDRESS                     0x000014
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_HW_MASK                     0xffffffff
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_SW_MASK                     0xffffffff
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RSTMASK                     0x0000ffff
#define HWSCH_EIFS_PIFS_BCN_SLOT_LIMIT_1_RESET                       0x0000005a

// 0x0018 (HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT)
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_EARLY_PKT_DET_MISS_LIMIT_MSB 31
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_EARLY_PKT_DET_MISS_LIMIT_LSB 20
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_EARLY_PKT_DET_MISS_LIMIT_MASK 0xfff00000
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_EARLY_PKT_DET_MISS_LIMIT_GET(x) (((x) & HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_EARLY_PKT_DET_MISS_LIMIT_MASK) >> HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_EARLY_PKT_DET_MISS_LIMIT_LSB)
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_EARLY_PKT_DET_MISS_LIMIT_SET(x) (((0x0 | (x)) << HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_EARLY_PKT_DET_MISS_LIMIT_LSB) & HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_EARLY_PKT_DET_MISS_LIMIT_MASK)
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_EARLY_PKT_DET_MISS_LIMIT_RESET 32
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RESERVED_0_MSB         19
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RESERVED_0_LSB         16
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RESERVED_0_MASK        0x000f0000
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RESERVED_0_GET(x)      (((x) & HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RESERVED_0_MASK) >> HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RESERVED_0_LSB)
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RESERVED_0_SET(x)      (((0x0 | (x)) << HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RESERVED_0_LSB) & HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RESERVED_0_MASK)
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RESERVED_0_RESET       0
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_BCN_SLOT_LIMIT_MSB 7
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_BCN_SLOT_LIMIT_LSB 0
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_BCN_SLOT_LIMIT_MASK 0x000000ff
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_BCN_SLOT_LIMIT_GET(x) (((x) & HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_BCN_SLOT_LIMIT_MASK) >> HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_BCN_SLOT_LIMIT_LSB)
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_BCN_SLOT_LIMIT_SET(x) (((0x0 | (x)) << HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_BCN_SLOT_LIMIT_LSB) & HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_BCN_SLOT_LIMIT_MASK)
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MTU_BCN_SLOT_LIMIT_RESET 20
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_ADDRESS                0x000018
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_HW_MASK                0xffff00ff
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_SW_MASK                0xffff00ff
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RSTMASK                0xfff000ff
#define HWSCH_SW_MTU_BCN_SLOT_USEC_SIFS_LIMIT_RESET                  0x02000014

// 0x001c (HWSCH_SW_MTU_MISC_LIMITS)
#define HWSCH_SW_MTU_MISC_LIMITS_RESERVED_0_MSB                      31
#define HWSCH_SW_MTU_MISC_LIMITS_RESERVED_0_LSB                      10
#define HWSCH_SW_MTU_MISC_LIMITS_RESERVED_0_MASK                     0xfffffc00
#define HWSCH_SW_MTU_MISC_LIMITS_RESERVED_0_GET(x)                   (((x) & HWSCH_SW_MTU_MISC_LIMITS_RESERVED_0_MASK) >> HWSCH_SW_MTU_MISC_LIMITS_RESERVED_0_LSB)
#define HWSCH_SW_MTU_MISC_LIMITS_RESERVED_0_SET(x)                   (((0x0 | (x)) << HWSCH_SW_MTU_MISC_LIMITS_RESERVED_0_LSB) & HWSCH_SW_MTU_MISC_LIMITS_RESERVED_0_MASK)
#define HWSCH_SW_MTU_MISC_LIMITS_RESERVED_0_RESET                    0
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_LIMIT_MSB          9
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_LIMIT_LSB          4
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_LIMIT_MASK         0x000003f0
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_LIMIT_GET(x)       (((x) & HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_LIMIT_MASK) >> HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_LIMIT_LSB)
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_LIMIT_SET(x)       (((0x0 | (x)) << HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_LIMIT_LSB) & HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_LIMIT_MASK)
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_LIMIT_RESET        32
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_PULSE_LIMIT_MSB    3
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_PULSE_LIMIT_LSB    0
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_PULSE_LIMIT_MASK   0x0000000f
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_PULSE_LIMIT_GET(x) (((x) & HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_PULSE_LIMIT_MASK) >> HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_PULSE_LIMIT_LSB)
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_PULSE_LIMIT_SET(x) (((0x0 | (x)) << HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_PULSE_LIMIT_LSB) & HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_PULSE_LIMIT_MASK)
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MTU_TXP_DELAY_PULSE_LIMIT_RESET  9
#define HWSCH_SW_MTU_MISC_LIMITS_ADDRESS                             0x00001c
#define HWSCH_SW_MTU_MISC_LIMITS_HW_MASK                             0xffffffff
#define HWSCH_SW_MTU_MISC_LIMITS_SW_MASK                             0xffffffff
#define HWSCH_SW_MTU_MISC_LIMITS_RSTMASK                             0x000003ff
#define HWSCH_SW_MTU_MISC_LIMITS_RESET                               0x00000209

// 0x0020 (HWSCH_NAV_CNT)
#define HWSCH_NAV_CNT_NAV_CNT_MSB                                    31
#define HWSCH_NAV_CNT_NAV_CNT_LSB                                    0
#define HWSCH_NAV_CNT_NAV_CNT_MASK                                   0xffffffff
#define HWSCH_NAV_CNT_NAV_CNT_GET(x)                                 (((x) & HWSCH_NAV_CNT_NAV_CNT_MASK) >> HWSCH_NAV_CNT_NAV_CNT_LSB)
#define HWSCH_NAV_CNT_NAV_CNT_SET(x)                                 (((0x0 | (x)) << HWSCH_NAV_CNT_NAV_CNT_LSB) & HWSCH_NAV_CNT_NAV_CNT_MASK)
#define HWSCH_NAV_CNT_NAV_CNT_RESET                                  255
#define HWSCH_NAV_CNT_ADDRESS                                        0x000020
#define HWSCH_NAV_CNT_HW_MASK                                        0xffffffff
#define HWSCH_NAV_CNT_SW_MASK                                        0xffffffff
#define HWSCH_NAV_CNT_RSTMASK                                        0xffffffff
#define HWSCH_NAV_CNT_RESET                                          0x000000ff

// 0x0024 (HWSCH_BKOF_CNT_0)
#define HWSCH_BKOF_CNT_0_BKOF_CNT_0_MSB                              15
#define HWSCH_BKOF_CNT_0_BKOF_CNT_0_LSB                              0
#define HWSCH_BKOF_CNT_0_BKOF_CNT_0_MASK                             0x0000ffff
#define HWSCH_BKOF_CNT_0_BKOF_CNT_0_GET(x)                           (((x) & HWSCH_BKOF_CNT_0_BKOF_CNT_0_MASK) >> HWSCH_BKOF_CNT_0_BKOF_CNT_0_LSB)
#define HWSCH_BKOF_CNT_0_BKOF_CNT_0_SET(x)                           (((0x0 | (x)) << HWSCH_BKOF_CNT_0_BKOF_CNT_0_LSB) & HWSCH_BKOF_CNT_0_BKOF_CNT_0_MASK)
#define HWSCH_BKOF_CNT_0_BKOF_CNT_0_RESET                            3
#define HWSCH_BKOF_CNT_0_ADDRESS                                     0x000024
#define HWSCH_BKOF_CNT_0_HW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_0_SW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_0_RSTMASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_0_RESET                                       0x00000003

// 0x0028 (HWSCH_BKOF_CNT_1)
#define HWSCH_BKOF_CNT_1_BKOF_CNT_1_MSB                              15
#define HWSCH_BKOF_CNT_1_BKOF_CNT_1_LSB                              0
#define HWSCH_BKOF_CNT_1_BKOF_CNT_1_MASK                             0x0000ffff
#define HWSCH_BKOF_CNT_1_BKOF_CNT_1_GET(x)                           (((x) & HWSCH_BKOF_CNT_1_BKOF_CNT_1_MASK) >> HWSCH_BKOF_CNT_1_BKOF_CNT_1_LSB)
#define HWSCH_BKOF_CNT_1_BKOF_CNT_1_SET(x)                           (((0x0 | (x)) << HWSCH_BKOF_CNT_1_BKOF_CNT_1_LSB) & HWSCH_BKOF_CNT_1_BKOF_CNT_1_MASK)
#define HWSCH_BKOF_CNT_1_BKOF_CNT_1_RESET                            4
#define HWSCH_BKOF_CNT_1_ADDRESS                                     0x000028
#define HWSCH_BKOF_CNT_1_HW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_1_SW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_1_RSTMASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_1_RESET                                       0x00000004

// 0x002c (HWSCH_BKOF_CNT_2)
#define HWSCH_BKOF_CNT_2_BKOF_CNT_2_MSB                              15
#define HWSCH_BKOF_CNT_2_BKOF_CNT_2_LSB                              0
#define HWSCH_BKOF_CNT_2_BKOF_CNT_2_MASK                             0x0000ffff
#define HWSCH_BKOF_CNT_2_BKOF_CNT_2_GET(x)                           (((x) & HWSCH_BKOF_CNT_2_BKOF_CNT_2_MASK) >> HWSCH_BKOF_CNT_2_BKOF_CNT_2_LSB)
#define HWSCH_BKOF_CNT_2_BKOF_CNT_2_SET(x)                           (((0x0 | (x)) << HWSCH_BKOF_CNT_2_BKOF_CNT_2_LSB) & HWSCH_BKOF_CNT_2_BKOF_CNT_2_MASK)
#define HWSCH_BKOF_CNT_2_BKOF_CNT_2_RESET                            7
#define HWSCH_BKOF_CNT_2_ADDRESS                                     0x00002c
#define HWSCH_BKOF_CNT_2_HW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_2_SW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_2_RSTMASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_2_RESET                                       0x00000007

// 0x0030 (HWSCH_BKOF_CNT_3)
#define HWSCH_BKOF_CNT_3_BKOF_CNT_3_MSB                              15
#define HWSCH_BKOF_CNT_3_BKOF_CNT_3_LSB                              0
#define HWSCH_BKOF_CNT_3_BKOF_CNT_3_MASK                             0x0000ffff
#define HWSCH_BKOF_CNT_3_BKOF_CNT_3_GET(x)                           (((x) & HWSCH_BKOF_CNT_3_BKOF_CNT_3_MASK) >> HWSCH_BKOF_CNT_3_BKOF_CNT_3_LSB)
#define HWSCH_BKOF_CNT_3_BKOF_CNT_3_SET(x)                           (((0x0 | (x)) << HWSCH_BKOF_CNT_3_BKOF_CNT_3_LSB) & HWSCH_BKOF_CNT_3_BKOF_CNT_3_MASK)
#define HWSCH_BKOF_CNT_3_BKOF_CNT_3_RESET                            1
#define HWSCH_BKOF_CNT_3_ADDRESS                                     0x000030
#define HWSCH_BKOF_CNT_3_HW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_3_SW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_3_RSTMASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_3_RESET                                       0x00000001

// 0x0034 (HWSCH_BKOF_CNT_4)
#define HWSCH_BKOF_CNT_4_BKOF_CNT_4_MSB                              15
#define HWSCH_BKOF_CNT_4_BKOF_CNT_4_LSB                              0
#define HWSCH_BKOF_CNT_4_BKOF_CNT_4_MASK                             0x0000ffff
#define HWSCH_BKOF_CNT_4_BKOF_CNT_4_GET(x)                           (((x) & HWSCH_BKOF_CNT_4_BKOF_CNT_4_MASK) >> HWSCH_BKOF_CNT_4_BKOF_CNT_4_LSB)
#define HWSCH_BKOF_CNT_4_BKOF_CNT_4_SET(x)                           (((0x0 | (x)) << HWSCH_BKOF_CNT_4_BKOF_CNT_4_LSB) & HWSCH_BKOF_CNT_4_BKOF_CNT_4_MASK)
#define HWSCH_BKOF_CNT_4_BKOF_CNT_4_RESET                            2
#define HWSCH_BKOF_CNT_4_ADDRESS                                     0x000034
#define HWSCH_BKOF_CNT_4_HW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_4_SW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_4_RSTMASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_4_RESET                                       0x00000002

// 0x0038 (HWSCH_BKOF_CNT_5)
#define HWSCH_BKOF_CNT_5_BKOF_CNT_5_MSB                              15
#define HWSCH_BKOF_CNT_5_BKOF_CNT_5_LSB                              0
#define HWSCH_BKOF_CNT_5_BKOF_CNT_5_MASK                             0x0000ffff
#define HWSCH_BKOF_CNT_5_BKOF_CNT_5_GET(x)                           (((x) & HWSCH_BKOF_CNT_5_BKOF_CNT_5_MASK) >> HWSCH_BKOF_CNT_5_BKOF_CNT_5_LSB)
#define HWSCH_BKOF_CNT_5_BKOF_CNT_5_SET(x)                           (((0x0 | (x)) << HWSCH_BKOF_CNT_5_BKOF_CNT_5_LSB) & HWSCH_BKOF_CNT_5_BKOF_CNT_5_MASK)
#define HWSCH_BKOF_CNT_5_BKOF_CNT_5_RESET                            5
#define HWSCH_BKOF_CNT_5_ADDRESS                                     0x000038
#define HWSCH_BKOF_CNT_5_HW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_5_SW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_5_RSTMASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_5_RESET                                       0x00000005

// 0x003c (HWSCH_BKOF_CNT_6)
#define HWSCH_BKOF_CNT_6_BKOF_CNT_6_MSB                              15
#define HWSCH_BKOF_CNT_6_BKOF_CNT_6_LSB                              0
#define HWSCH_BKOF_CNT_6_BKOF_CNT_6_MASK                             0x0000ffff
#define HWSCH_BKOF_CNT_6_BKOF_CNT_6_GET(x)                           (((x) & HWSCH_BKOF_CNT_6_BKOF_CNT_6_MASK) >> HWSCH_BKOF_CNT_6_BKOF_CNT_6_LSB)
#define HWSCH_BKOF_CNT_6_BKOF_CNT_6_SET(x)                           (((0x0 | (x)) << HWSCH_BKOF_CNT_6_BKOF_CNT_6_LSB) & HWSCH_BKOF_CNT_6_BKOF_CNT_6_MASK)
#define HWSCH_BKOF_CNT_6_BKOF_CNT_6_RESET                            6
#define HWSCH_BKOF_CNT_6_ADDRESS                                     0x00003c
#define HWSCH_BKOF_CNT_6_HW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_6_SW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_6_RSTMASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_6_RESET                                       0x00000006

// 0x0040 (HWSCH_BKOF_CNT_7)
#define HWSCH_BKOF_CNT_7_BKOF_CNT_7_MSB                              15
#define HWSCH_BKOF_CNT_7_BKOF_CNT_7_LSB                              0
#define HWSCH_BKOF_CNT_7_BKOF_CNT_7_MASK                             0x0000ffff
#define HWSCH_BKOF_CNT_7_BKOF_CNT_7_GET(x)                           (((x) & HWSCH_BKOF_CNT_7_BKOF_CNT_7_MASK) >> HWSCH_BKOF_CNT_7_BKOF_CNT_7_LSB)
#define HWSCH_BKOF_CNT_7_BKOF_CNT_7_SET(x)                           (((0x0 | (x)) << HWSCH_BKOF_CNT_7_BKOF_CNT_7_LSB) & HWSCH_BKOF_CNT_7_BKOF_CNT_7_MASK)
#define HWSCH_BKOF_CNT_7_BKOF_CNT_7_RESET                            0
#define HWSCH_BKOF_CNT_7_ADDRESS                                     0x000040
#define HWSCH_BKOF_CNT_7_HW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_7_SW_MASK                                     0x0000ffff
#define HWSCH_BKOF_CNT_7_RSTMASK                                     0x00000000
#define HWSCH_BKOF_CNT_7_RESET                                       0x00000000

// 0x0044 (HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_UPDATE_VALID_MSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_UPDATE_VALID_LSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_UPDATE_VALID_MASK 0x00080000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_UPDATE_VALID_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_UPDATE_VALID_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_UPDATE_VALID_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_UPDATE_VALID_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_UPDATE_VALID_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_UPDATE_VALID_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_UPDATE_VALID_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_ACTION_0_MSB    18
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_ACTION_0_LSB    17
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_ACTION_0_MASK   0x00060000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_ACTION_0_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_ACTION_0_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_ACTION_0_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_ACTION_0_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_ACTION_0_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_ACTION_0_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_ACTION_0_RESET  0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_WAIT_DONE_P_0_MSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_WAIT_DONE_P_0_LSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_WAIT_DONE_P_0_MASK 0x00010000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_WAIT_DONE_P_0_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_WAIT_DONE_P_0_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_WAIT_DONE_P_0_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_WAIT_DONE_P_0_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_WAIT_DONE_P_0_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_WAIT_DONE_P_0_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_WAIT_DONE_P_0_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_REG_0_MSB       15
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_REG_0_LSB       0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_REG_0_MASK      0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_REG_0_GET(x)    (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_REG_0_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_REG_0_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_REG_0_SET(x)    (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_REG_0_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_REG_0_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MTU_CW_REG_0_RESET     7
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_ADDRESS                   0x000044
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_HW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_SW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_RSTMASK                   0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_0_RESET                     0x00000007

// 0x0048 (HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_UPDATE_VALID_MSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_UPDATE_VALID_LSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_UPDATE_VALID_MASK 0x00080000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_UPDATE_VALID_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_UPDATE_VALID_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_UPDATE_VALID_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_UPDATE_VALID_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_UPDATE_VALID_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_UPDATE_VALID_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_UPDATE_VALID_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_ACTION_1_MSB    18
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_ACTION_1_LSB    17
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_ACTION_1_MASK   0x00060000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_ACTION_1_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_ACTION_1_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_ACTION_1_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_ACTION_1_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_ACTION_1_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_ACTION_1_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_ACTION_1_RESET  0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_WAIT_DONE_P_1_MSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_WAIT_DONE_P_1_LSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_WAIT_DONE_P_1_MASK 0x00010000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_WAIT_DONE_P_1_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_WAIT_DONE_P_1_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_WAIT_DONE_P_1_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_WAIT_DONE_P_1_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_WAIT_DONE_P_1_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_WAIT_DONE_P_1_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_WAIT_DONE_P_1_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_REG_1_MSB       15
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_REG_1_LSB       0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_REG_1_MASK      0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_REG_1_GET(x)    (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_REG_1_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_REG_1_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_REG_1_SET(x)    (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_REG_1_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_REG_1_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MTU_CW_REG_1_RESET     7
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_ADDRESS                   0x000048
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_HW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_SW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_RSTMASK                   0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_1_RESET                     0x00000007

// 0x004c (HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_UPDATE_VALID_MSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_UPDATE_VALID_LSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_UPDATE_VALID_MASK 0x00080000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_UPDATE_VALID_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_UPDATE_VALID_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_UPDATE_VALID_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_UPDATE_VALID_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_UPDATE_VALID_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_UPDATE_VALID_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_UPDATE_VALID_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_ACTION_2_MSB    18
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_ACTION_2_LSB    17
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_ACTION_2_MASK   0x00060000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_ACTION_2_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_ACTION_2_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_ACTION_2_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_ACTION_2_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_ACTION_2_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_ACTION_2_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_ACTION_2_RESET  0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_WAIT_DONE_P_2_MSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_WAIT_DONE_P_2_LSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_WAIT_DONE_P_2_MASK 0x00010000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_WAIT_DONE_P_2_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_WAIT_DONE_P_2_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_WAIT_DONE_P_2_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_WAIT_DONE_P_2_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_WAIT_DONE_P_2_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_WAIT_DONE_P_2_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_WAIT_DONE_P_2_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_REG_2_MSB       15
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_REG_2_LSB       0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_REG_2_MASK      0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_REG_2_GET(x)    (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_REG_2_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_REG_2_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_REG_2_SET(x)    (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_REG_2_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_REG_2_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MTU_CW_REG_2_RESET     7
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_ADDRESS                   0x00004c
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_HW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_SW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_RSTMASK                   0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_2_RESET                     0x00000007

// 0x0050 (HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_UPDATE_VALID_MSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_UPDATE_VALID_LSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_UPDATE_VALID_MASK 0x00080000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_UPDATE_VALID_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_UPDATE_VALID_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_UPDATE_VALID_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_UPDATE_VALID_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_UPDATE_VALID_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_UPDATE_VALID_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_UPDATE_VALID_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_ACTION_3_MSB    18
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_ACTION_3_LSB    17
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_ACTION_3_MASK   0x00060000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_ACTION_3_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_ACTION_3_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_ACTION_3_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_ACTION_3_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_ACTION_3_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_ACTION_3_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_ACTION_3_RESET  0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_WAIT_DONE_P_3_MSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_WAIT_DONE_P_3_LSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_WAIT_DONE_P_3_MASK 0x00010000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_WAIT_DONE_P_3_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_WAIT_DONE_P_3_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_WAIT_DONE_P_3_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_WAIT_DONE_P_3_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_WAIT_DONE_P_3_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_WAIT_DONE_P_3_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_WAIT_DONE_P_3_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_REG_3_MSB       15
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_REG_3_LSB       0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_REG_3_MASK      0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_REG_3_GET(x)    (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_REG_3_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_REG_3_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_REG_3_SET(x)    (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_REG_3_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_REG_3_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MTU_CW_REG_3_RESET     7
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_ADDRESS                   0x000050
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_HW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_SW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_RSTMASK                   0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_3_RESET                     0x00000007

// 0x0054 (HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_UPDATE_VALID_MSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_UPDATE_VALID_LSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_UPDATE_VALID_MASK 0x00080000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_UPDATE_VALID_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_UPDATE_VALID_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_UPDATE_VALID_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_UPDATE_VALID_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_UPDATE_VALID_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_UPDATE_VALID_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_UPDATE_VALID_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_ACTION_4_MSB    18
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_ACTION_4_LSB    17
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_ACTION_4_MASK   0x00060000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_ACTION_4_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_ACTION_4_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_ACTION_4_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_ACTION_4_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_ACTION_4_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_ACTION_4_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_ACTION_4_RESET  0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_WAIT_DONE_P_4_MSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_WAIT_DONE_P_4_LSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_WAIT_DONE_P_4_MASK 0x00010000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_WAIT_DONE_P_4_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_WAIT_DONE_P_4_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_WAIT_DONE_P_4_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_WAIT_DONE_P_4_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_WAIT_DONE_P_4_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_WAIT_DONE_P_4_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_WAIT_DONE_P_4_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_REG_4_MSB       15
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_REG_4_LSB       0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_REG_4_MASK      0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_REG_4_GET(x)    (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_REG_4_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_REG_4_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_REG_4_SET(x)    (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_REG_4_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_REG_4_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MTU_CW_REG_4_RESET     7
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_ADDRESS                   0x000054
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_HW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_SW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_RSTMASK                   0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_4_RESET                     0x00000007

// 0x0058 (HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_UPDATE_VALID_MSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_UPDATE_VALID_LSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_UPDATE_VALID_MASK 0x00080000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_UPDATE_VALID_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_UPDATE_VALID_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_UPDATE_VALID_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_UPDATE_VALID_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_UPDATE_VALID_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_UPDATE_VALID_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_UPDATE_VALID_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_ACTION_5_MSB    18
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_ACTION_5_LSB    17
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_ACTION_5_MASK   0x00060000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_ACTION_5_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_ACTION_5_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_ACTION_5_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_ACTION_5_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_ACTION_5_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_ACTION_5_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_ACTION_5_RESET  0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_WAIT_DONE_P_5_MSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_WAIT_DONE_P_5_LSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_WAIT_DONE_P_5_MASK 0x00010000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_WAIT_DONE_P_5_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_WAIT_DONE_P_5_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_WAIT_DONE_P_5_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_WAIT_DONE_P_5_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_WAIT_DONE_P_5_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_WAIT_DONE_P_5_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_WAIT_DONE_P_5_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_REG_5_MSB       15
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_REG_5_LSB       0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_REG_5_MASK      0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_REG_5_GET(x)    (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_REG_5_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_REG_5_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_REG_5_SET(x)    (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_REG_5_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_REG_5_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MTU_CW_REG_5_RESET     7
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_ADDRESS                   0x000058
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_HW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_SW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_RSTMASK                   0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_5_RESET                     0x00000007

// 0x005c (HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_UPDATE_VALID_MSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_UPDATE_VALID_LSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_UPDATE_VALID_MASK 0x00080000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_UPDATE_VALID_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_UPDATE_VALID_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_UPDATE_VALID_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_UPDATE_VALID_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_UPDATE_VALID_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_UPDATE_VALID_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_UPDATE_VALID_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_ACTION_6_MSB    18
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_ACTION_6_LSB    17
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_ACTION_6_MASK   0x00060000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_ACTION_6_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_ACTION_6_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_ACTION_6_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_ACTION_6_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_ACTION_6_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_ACTION_6_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_ACTION_6_RESET  0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_WAIT_DONE_P_6_MSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_WAIT_DONE_P_6_LSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_WAIT_DONE_P_6_MASK 0x00010000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_WAIT_DONE_P_6_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_WAIT_DONE_P_6_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_WAIT_DONE_P_6_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_WAIT_DONE_P_6_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_WAIT_DONE_P_6_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_WAIT_DONE_P_6_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_WAIT_DONE_P_6_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_REG_6_MSB       15
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_REG_6_LSB       0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_REG_6_MASK      0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_REG_6_GET(x)    (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_REG_6_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_REG_6_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_REG_6_SET(x)    (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_REG_6_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_REG_6_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MTU_CW_REG_6_RESET     7
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_ADDRESS                   0x00005c
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_HW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_SW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_RSTMASK                   0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_6_RESET                     0x00000007

// 0x0060 (HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_UPDATE_VALID_MSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_UPDATE_VALID_LSB 19
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_UPDATE_VALID_MASK 0x00080000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_UPDATE_VALID_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_UPDATE_VALID_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_UPDATE_VALID_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_UPDATE_VALID_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_UPDATE_VALID_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_UPDATE_VALID_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_UPDATE_VALID_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_ACTION_7_MSB    18
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_ACTION_7_LSB    17
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_ACTION_7_MASK   0x00060000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_ACTION_7_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_ACTION_7_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_ACTION_7_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_ACTION_7_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_ACTION_7_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_ACTION_7_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_ACTION_7_RESET  0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_WAIT_DONE_P_7_MSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_WAIT_DONE_P_7_LSB  16
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_WAIT_DONE_P_7_MASK 0x00010000
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_WAIT_DONE_P_7_GET(x) (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_WAIT_DONE_P_7_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_WAIT_DONE_P_7_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_WAIT_DONE_P_7_SET(x) (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_WAIT_DONE_P_7_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_WAIT_DONE_P_7_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_WAIT_DONE_P_7_RESET 0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_REG_7_MSB       15
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_REG_7_LSB       0
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_REG_7_MASK      0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_REG_7_GET(x)    (((x) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_REG_7_MASK) >> HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_REG_7_LSB)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_REG_7_SET(x)    (((0x0 | (x)) << HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_REG_7_LSB) & HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_REG_7_MASK)
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MTU_CW_REG_7_RESET     7
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_ADDRESS                   0x000060
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_HW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_SW_MASK                   0x000fffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_RSTMASK                   0x0000ffff
#define HWSCH_CW_REG_CONTROL_FOR_BACKOFF_7_RESET                     0x00000007

// 0x0064 (HWSCH_SW_CW_MIN_CW_MAX_0)
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MAX_0_MSB                     31
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MAX_0_LSB                     16
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MAX_0_MASK                    0xffff0000
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MAX_0_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MAX_0_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MAX_0_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MAX_0_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MAX_0_LSB) & HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MAX_0_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MAX_0_RESET                   1023
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MIN_0_MSB                     15
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MIN_0_LSB                     0
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MIN_0_MASK                    0x0000ffff
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MIN_0_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MIN_0_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MIN_0_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MIN_0_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MIN_0_LSB) & HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MIN_0_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_CW_MIN_0_RESET                   15
#define HWSCH_SW_CW_MIN_CW_MAX_0_ADDRESS                             0x000064
#define HWSCH_SW_CW_MIN_CW_MAX_0_HW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_0_SW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_0_RSTMASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_0_RESET                               0x03ff000f

// 0x0068 (HWSCH_SW_CW_MIN_CW_MAX_1)
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MAX_1_MSB                     31
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MAX_1_LSB                     16
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MAX_1_MASK                    0xffff0000
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MAX_1_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MAX_1_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MAX_1_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MAX_1_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MAX_1_LSB) & HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MAX_1_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MAX_1_RESET                   1023
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MIN_1_MSB                     15
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MIN_1_LSB                     0
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MIN_1_MASK                    0x0000ffff
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MIN_1_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MIN_1_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MIN_1_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MIN_1_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MIN_1_LSB) & HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MIN_1_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_CW_MIN_1_RESET                   15
#define HWSCH_SW_CW_MIN_CW_MAX_1_ADDRESS                             0x000068
#define HWSCH_SW_CW_MIN_CW_MAX_1_HW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_1_SW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_1_RSTMASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_1_RESET                               0x03ff000f

// 0x006c (HWSCH_SW_CW_MIN_CW_MAX_2)
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MAX_2_MSB                     31
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MAX_2_LSB                     16
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MAX_2_MASK                    0xffff0000
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MAX_2_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MAX_2_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MAX_2_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MAX_2_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MAX_2_LSB) & HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MAX_2_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MAX_2_RESET                   7
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MIN_2_MSB                     15
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MIN_2_LSB                     0
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MIN_2_MASK                    0x0000ffff
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MIN_2_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MIN_2_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MIN_2_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MIN_2_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MIN_2_LSB) & HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MIN_2_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_CW_MIN_2_RESET                   3
#define HWSCH_SW_CW_MIN_CW_MAX_2_ADDRESS                             0x00006c
#define HWSCH_SW_CW_MIN_CW_MAX_2_HW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_2_SW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_2_RSTMASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_2_RESET                               0x00070003

// 0x0070 (HWSCH_SW_CW_MIN_CW_MAX_3)
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MAX_3_MSB                     31
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MAX_3_LSB                     16
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MAX_3_MASK                    0xffff0000
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MAX_3_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MAX_3_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MAX_3_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MAX_3_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MAX_3_LSB) & HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MAX_3_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MAX_3_RESET                   7
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MIN_3_MSB                     15
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MIN_3_LSB                     0
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MIN_3_MASK                    0x0000ffff
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MIN_3_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MIN_3_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MIN_3_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MIN_3_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MIN_3_LSB) & HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MIN_3_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_CW_MIN_3_RESET                   3
#define HWSCH_SW_CW_MIN_CW_MAX_3_ADDRESS                             0x000070
#define HWSCH_SW_CW_MIN_CW_MAX_3_HW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_3_SW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_3_RSTMASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_3_RESET                               0x00070003

// 0x0074 (HWSCH_SW_CW_MIN_CW_MAX_4)
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MAX_4_MSB                     31
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MAX_4_LSB                     16
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MAX_4_MASK                    0xffff0000
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MAX_4_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MAX_4_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MAX_4_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MAX_4_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MAX_4_LSB) & HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MAX_4_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MAX_4_RESET                   7
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MIN_4_MSB                     15
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MIN_4_LSB                     0
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MIN_4_MASK                    0x0000ffff
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MIN_4_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MIN_4_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MIN_4_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MIN_4_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MIN_4_LSB) & HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MIN_4_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_CW_MIN_4_RESET                   3
#define HWSCH_SW_CW_MIN_CW_MAX_4_ADDRESS                             0x000074
#define HWSCH_SW_CW_MIN_CW_MAX_4_HW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_4_SW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_4_RSTMASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_4_RESET                               0x00070003

// 0x0078 (HWSCH_SW_CW_MIN_CW_MAX_5)
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MAX_5_MSB                     31
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MAX_5_LSB                     16
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MAX_5_MASK                    0xffff0000
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MAX_5_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MAX_5_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MAX_5_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MAX_5_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MAX_5_LSB) & HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MAX_5_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MAX_5_RESET                   15
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MIN_5_MSB                     15
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MIN_5_LSB                     0
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MIN_5_MASK                    0x0000ffff
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MIN_5_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MIN_5_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MIN_5_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MIN_5_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MIN_5_LSB) & HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MIN_5_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_CW_MIN_5_RESET                   7
#define HWSCH_SW_CW_MIN_CW_MAX_5_ADDRESS                             0x000078
#define HWSCH_SW_CW_MIN_CW_MAX_5_HW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_5_SW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_5_RSTMASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_5_RESET                               0x000f0007

// 0x007c (HWSCH_SW_CW_MIN_CW_MAX_6)
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MAX_6_MSB                     31
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MAX_6_LSB                     16
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MAX_6_MASK                    0xffff0000
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MAX_6_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MAX_6_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MAX_6_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MAX_6_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MAX_6_LSB) & HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MAX_6_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MAX_6_RESET                   1023
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MIN_6_MSB                     15
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MIN_6_LSB                     0
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MIN_6_MASK                    0x0000ffff
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MIN_6_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MIN_6_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MIN_6_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MIN_6_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MIN_6_LSB) & HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MIN_6_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_CW_MIN_6_RESET                   15
#define HWSCH_SW_CW_MIN_CW_MAX_6_ADDRESS                             0x00007c
#define HWSCH_SW_CW_MIN_CW_MAX_6_HW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_6_SW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_6_RSTMASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_6_RESET                               0x03ff000f

// 0x0080 (HWSCH_SW_CW_MIN_CW_MAX_7)
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MAX_7_MSB                     31
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MAX_7_LSB                     16
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MAX_7_MASK                    0xffff0000
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MAX_7_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MAX_7_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MAX_7_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MAX_7_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MAX_7_LSB) & HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MAX_7_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MAX_7_RESET                   1023
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MIN_7_MSB                     15
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MIN_7_LSB                     0
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MIN_7_MASK                    0x0000ffff
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MIN_7_GET(x)                  (((x) & HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MIN_7_MASK) >> HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MIN_7_LSB)
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MIN_7_SET(x)                  (((0x0 | (x)) << HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MIN_7_LSB) & HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MIN_7_MASK)
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_CW_MIN_7_RESET                   15
#define HWSCH_SW_CW_MIN_CW_MAX_7_ADDRESS                             0x000080
#define HWSCH_SW_CW_MIN_CW_MAX_7_HW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_7_SW_MASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_7_RSTMASK                             0xffffffff
#define HWSCH_SW_CW_MIN_CW_MAX_7_RESET                               0x03ff000f

// 0x0084 (HWSCH_BKOF_CONTROL)
#define HWSCH_BKOF_CONTROL_RESERVED_0_MSB                            31
#define HWSCH_BKOF_CONTROL_RESERVED_0_LSB                            16
#define HWSCH_BKOF_CONTROL_RESERVED_0_MASK                           0xffff0000
#define HWSCH_BKOF_CONTROL_RESERVED_0_GET(x)                         (((x) & HWSCH_BKOF_CONTROL_RESERVED_0_MASK) >> HWSCH_BKOF_CONTROL_RESERVED_0_LSB)
#define HWSCH_BKOF_CONTROL_RESERVED_0_SET(x)                         (((0x0 | (x)) << HWSCH_BKOF_CONTROL_RESERVED_0_LSB) & HWSCH_BKOF_CONTROL_RESERVED_0_MASK)
#define HWSCH_BKOF_CONTROL_RESERVED_0_RESET                          0
#define HWSCH_BKOF_CONTROL_SW_MTU_STALL_BKOF_MSB                     15
#define HWSCH_BKOF_CONTROL_SW_MTU_STALL_BKOF_LSB                     8
#define HWSCH_BKOF_CONTROL_SW_MTU_STALL_BKOF_MASK                    0x0000ff00
#define HWSCH_BKOF_CONTROL_SW_MTU_STALL_BKOF_GET(x)                  (((x) & HWSCH_BKOF_CONTROL_SW_MTU_STALL_BKOF_MASK) >> HWSCH_BKOF_CONTROL_SW_MTU_STALL_BKOF_LSB)
#define HWSCH_BKOF_CONTROL_SW_MTU_STALL_BKOF_SET(x)                  (((0x0 | (x)) << HWSCH_BKOF_CONTROL_SW_MTU_STALL_BKOF_LSB) & HWSCH_BKOF_CONTROL_SW_MTU_STALL_BKOF_MASK)
#define HWSCH_BKOF_CONTROL_SW_MTU_STALL_BKOF_RESET                   0
#define HWSCH_BKOF_CONTROL_SW_MTU_USE_SW_BKOF_COUNTER_MSB            7
#define HWSCH_BKOF_CONTROL_SW_MTU_USE_SW_BKOF_COUNTER_LSB            0
#define HWSCH_BKOF_CONTROL_SW_MTU_USE_SW_BKOF_COUNTER_MASK           0x000000ff
#define HWSCH_BKOF_CONTROL_SW_MTU_USE_SW_BKOF_COUNTER_GET(x)         (((x) & HWSCH_BKOF_CONTROL_SW_MTU_USE_SW_BKOF_COUNTER_MASK) >> HWSCH_BKOF_CONTROL_SW_MTU_USE_SW_BKOF_COUNTER_LSB)
#define HWSCH_BKOF_CONTROL_SW_MTU_USE_SW_BKOF_COUNTER_SET(x)         (((0x0 | (x)) << HWSCH_BKOF_CONTROL_SW_MTU_USE_SW_BKOF_COUNTER_LSB) & HWSCH_BKOF_CONTROL_SW_MTU_USE_SW_BKOF_COUNTER_MASK)
#define HWSCH_BKOF_CONTROL_SW_MTU_USE_SW_BKOF_COUNTER_RESET          0
#define HWSCH_BKOF_CONTROL_ADDRESS                                   0x000084
#define HWSCH_BKOF_CONTROL_HW_MASK                                   0xffffffff
#define HWSCH_BKOF_CONTROL_SW_MASK                                   0xffffffff
#define HWSCH_BKOF_CONTROL_RSTMASK                                   0x00000000
#define HWSCH_BKOF_CONTROL_RESET                                     0x00000000

// 0x0088 (HWSCH_BKOF_CONTROL_1)
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_CSI_BKOF_EN_MSB         31
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_CSI_BKOF_EN_LSB         31
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_CSI_BKOF_EN_MASK        0x80000000
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_CSI_BKOF_EN_GET(x)      (((x) & HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_CSI_BKOF_EN_MASK) >> HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_CSI_BKOF_EN_LSB)
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_CSI_BKOF_EN_SET(x)      (((0x0 | (x)) << HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_CSI_BKOF_EN_LSB) & HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_CSI_BKOF_EN_MASK)
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_CSI_BKOF_EN_RESET       0
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_QOSNULL_BKOF_EN_MSB     30
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_QOSNULL_BKOF_EN_LSB     30
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_QOSNULL_BKOF_EN_MASK    0x40000000
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_QOSNULL_BKOF_EN_GET(x)  (((x) & HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_QOSNULL_BKOF_EN_MASK) >> HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_QOSNULL_BKOF_EN_LSB)
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_QOSNULL_BKOF_EN_SET(x)  (((0x0 | (x)) << HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_QOSNULL_BKOF_EN_LSB) & HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_QOSNULL_BKOF_EN_MASK)
#define HWSCH_BKOF_CONTROL_1_SW_MTU_CONSIDER_QOSNULL_BKOF_EN_RESET   0
#define HWSCH_BKOF_CONTROL_1_RESERVED_0_MSB                          29
#define HWSCH_BKOF_CONTROL_1_RESERVED_0_LSB                          8
#define HWSCH_BKOF_CONTROL_1_RESERVED_0_MASK                         0x3fffff00
#define HWSCH_BKOF_CONTROL_1_RESERVED_0_GET(x)                       (((x) & HWSCH_BKOF_CONTROL_1_RESERVED_0_MASK) >> HWSCH_BKOF_CONTROL_1_RESERVED_0_LSB)
#define HWSCH_BKOF_CONTROL_1_RESERVED_0_SET(x)                       (((0x0 | (x)) << HWSCH_BKOF_CONTROL_1_RESERVED_0_LSB) & HWSCH_BKOF_CONTROL_1_RESERVED_0_MASK)
#define HWSCH_BKOF_CONTROL_1_RESERVED_0_RESET                        0
#define HWSCH_BKOF_CONTROL_1_SW_MTU_QUEUE_DATA_AVAIL_MSB             7
#define HWSCH_BKOF_CONTROL_1_SW_MTU_QUEUE_DATA_AVAIL_LSB             0
#define HWSCH_BKOF_CONTROL_1_SW_MTU_QUEUE_DATA_AVAIL_MASK            0x000000ff
#define HWSCH_BKOF_CONTROL_1_SW_MTU_QUEUE_DATA_AVAIL_GET(x)          (((x) & HWSCH_BKOF_CONTROL_1_SW_MTU_QUEUE_DATA_AVAIL_MASK) >> HWSCH_BKOF_CONTROL_1_SW_MTU_QUEUE_DATA_AVAIL_LSB)
#define HWSCH_BKOF_CONTROL_1_SW_MTU_QUEUE_DATA_AVAIL_SET(x)          (((0x0 | (x)) << HWSCH_BKOF_CONTROL_1_SW_MTU_QUEUE_DATA_AVAIL_LSB) & HWSCH_BKOF_CONTROL_1_SW_MTU_QUEUE_DATA_AVAIL_MASK)
#define HWSCH_BKOF_CONTROL_1_SW_MTU_QUEUE_DATA_AVAIL_RESET           0
#define HWSCH_BKOF_CONTROL_1_ADDRESS                                 0x000088
#define HWSCH_BKOF_CONTROL_1_HW_MASK                                 0xffffffff
#define HWSCH_BKOF_CONTROL_1_SW_MASK                                 0xffffffff
#define HWSCH_BKOF_CONTROL_1_RSTMASK                                 0x00000000
#define HWSCH_BKOF_CONTROL_1_RESET                                   0x00000000

// 0x008c (HWSCH_MTU_INTERRUPT_STATUS)
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_1_MSB                    31
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_1_LSB                    24
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_1_MASK                   0xff000000
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_1_GET(x)                 (((x) & HWSCH_MTU_INTERRUPT_STATUS_RESERVED_1_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_RESERVED_1_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_1_SET(x)                 (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_RESERVED_1_LSB) & HWSCH_MTU_INTERRUPT_STATUS_RESERVED_1_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_1_RESET                  0
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG7_MSB        23
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG7_LSB        23
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG7_MASK       0x00800000
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG7_GET(x)     (((x) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG7_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG7_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG7_SET(x)     (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG7_LSB) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG7_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG7_RESET      0
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG6_MSB        22
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG6_LSB        22
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG6_MASK       0x00400000
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG6_GET(x)     (((x) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG6_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG6_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG6_SET(x)     (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG6_LSB) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG6_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG6_RESET      0
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG5_MSB        21
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG5_LSB        21
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG5_MASK       0x00200000
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG5_GET(x)     (((x) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG5_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG5_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG5_SET(x)     (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG5_LSB) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG5_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG5_RESET      0
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG4_MSB        20
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG4_LSB        20
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG4_MASK       0x00100000
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG4_GET(x)     (((x) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG4_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG4_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG4_SET(x)     (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG4_LSB) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG4_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG4_RESET      0
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG3_MSB        19
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG3_LSB        19
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG3_MASK       0x00080000
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG3_GET(x)     (((x) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG3_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG3_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG3_SET(x)     (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG3_LSB) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG3_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG3_RESET      0
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG2_MSB        18
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG2_LSB        18
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG2_MASK       0x00040000
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG2_GET(x)     (((x) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG2_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG2_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG2_SET(x)     (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG2_LSB) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG2_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG2_RESET      0
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG1_MSB        17
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG1_LSB        17
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG1_MASK       0x00020000
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG1_GET(x)     (((x) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG1_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG1_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG1_SET(x)     (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG1_LSB) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG1_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG1_RESET      0
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG0_MSB        16
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG0_LSB        16
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG0_MASK       0x00010000
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG0_GET(x)     (((x) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG0_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG0_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG0_SET(x)     (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG0_LSB) & HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG0_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_MTU_MCU_BKOF_INT_FLAG0_RESET      0
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_0_MSB                    15
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_0_LSB                    5
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_0_MASK                   0x0000ffe0
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_0_GET(x)                 (((x) & HWSCH_MTU_INTERRUPT_STATUS_RESERVED_0_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_RESERVED_0_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_RESERVED_0_LSB) & HWSCH_MTU_INTERRUPT_STATUS_RESERVED_0_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_RESERVED_0_RESET                  0
#define HWSCH_MTU_INTERRUPT_STATUS_QUATERNARY_CCA_TO_MSB             4
#define HWSCH_MTU_INTERRUPT_STATUS_QUATERNARY_CCA_TO_LSB             4
#define HWSCH_MTU_INTERRUPT_STATUS_QUATERNARY_CCA_TO_MASK            0x00000010
#define HWSCH_MTU_INTERRUPT_STATUS_QUATERNARY_CCA_TO_GET(x)          (((x) & HWSCH_MTU_INTERRUPT_STATUS_QUATERNARY_CCA_TO_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_QUATERNARY_CCA_TO_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_QUATERNARY_CCA_TO_SET(x)          (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_QUATERNARY_CCA_TO_LSB) & HWSCH_MTU_INTERRUPT_STATUS_QUATERNARY_CCA_TO_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_QUATERNARY_CCA_TO_RESET           0
#define HWSCH_MTU_INTERRUPT_STATUS_TERTIARY_CCA_TO_MSB               3
#define HWSCH_MTU_INTERRUPT_STATUS_TERTIARY_CCA_TO_LSB               3
#define HWSCH_MTU_INTERRUPT_STATUS_TERTIARY_CCA_TO_MASK              0x00000008
#define HWSCH_MTU_INTERRUPT_STATUS_TERTIARY_CCA_TO_GET(x)            (((x) & HWSCH_MTU_INTERRUPT_STATUS_TERTIARY_CCA_TO_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_TERTIARY_CCA_TO_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_TERTIARY_CCA_TO_SET(x)            (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_TERTIARY_CCA_TO_LSB) & HWSCH_MTU_INTERRUPT_STATUS_TERTIARY_CCA_TO_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_TERTIARY_CCA_TO_RESET             0
#define HWSCH_MTU_INTERRUPT_STATUS_SECONDARY_CCA_TO_MSB              2
#define HWSCH_MTU_INTERRUPT_STATUS_SECONDARY_CCA_TO_LSB              2
#define HWSCH_MTU_INTERRUPT_STATUS_SECONDARY_CCA_TO_MASK             0x00000004
#define HWSCH_MTU_INTERRUPT_STATUS_SECONDARY_CCA_TO_GET(x)           (((x) & HWSCH_MTU_INTERRUPT_STATUS_SECONDARY_CCA_TO_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_SECONDARY_CCA_TO_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_SECONDARY_CCA_TO_SET(x)           (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_SECONDARY_CCA_TO_LSB) & HWSCH_MTU_INTERRUPT_STATUS_SECONDARY_CCA_TO_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_SECONDARY_CCA_TO_RESET            0
#define HWSCH_MTU_INTERRUPT_STATUS_SIFS_TO_MSB                       1
#define HWSCH_MTU_INTERRUPT_STATUS_SIFS_TO_LSB                       1
#define HWSCH_MTU_INTERRUPT_STATUS_SIFS_TO_MASK                      0x00000002
#define HWSCH_MTU_INTERRUPT_STATUS_SIFS_TO_GET(x)                    (((x) & HWSCH_MTU_INTERRUPT_STATUS_SIFS_TO_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_SIFS_TO_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_SIFS_TO_SET(x)                    (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_SIFS_TO_LSB) & HWSCH_MTU_INTERRUPT_STATUS_SIFS_TO_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_SIFS_TO_RESET                     0
#define HWSCH_MTU_INTERRUPT_STATUS_PIFS_TO_MSB                       0
#define HWSCH_MTU_INTERRUPT_STATUS_PIFS_TO_LSB                       0
#define HWSCH_MTU_INTERRUPT_STATUS_PIFS_TO_MASK                      0x00000001
#define HWSCH_MTU_INTERRUPT_STATUS_PIFS_TO_GET(x)                    (((x) & HWSCH_MTU_INTERRUPT_STATUS_PIFS_TO_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_PIFS_TO_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_PIFS_TO_SET(x)                    (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_PIFS_TO_LSB) & HWSCH_MTU_INTERRUPT_STATUS_PIFS_TO_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_PIFS_TO_RESET                     0
#define HWSCH_MTU_INTERRUPT_STATUS_ADDRESS                           0x00008c
#define HWSCH_MTU_INTERRUPT_STATUS_HW_MASK                           0xffffffff
#define HWSCH_MTU_INTERRUPT_STATUS_SW_MASK                           0xffffffff
#define HWSCH_MTU_INTERRUPT_STATUS_RSTMASK                           0x00000000
#define HWSCH_MTU_INTERRUPT_STATUS_RESET                             0x00000000

// 0x0090 (HWSCH_MTU_INTERRUPT_STATUS_1)
#define HWSCH_MTU_INTERRUPT_STATUS_1_RESERVED_0_MSB                  31
#define HWSCH_MTU_INTERRUPT_STATUS_1_RESERVED_0_LSB                  16
#define HWSCH_MTU_INTERRUPT_STATUS_1_RESERVED_0_MASK                 0xffff0000
#define HWSCH_MTU_INTERRUPT_STATUS_1_RESERVED_0_GET(x)               (((x) & HWSCH_MTU_INTERRUPT_STATUS_1_RESERVED_0_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_1_RESERVED_0_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_1_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_1_RESERVED_0_LSB) & HWSCH_MTU_INTERRUPT_STATUS_1_RESERVED_0_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_1_RESERVED_0_RESET                0
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE7_MSB           15
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE7_LSB           14
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE7_MASK          0x0000c000
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE7_GET(x)        (((x) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE7_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE7_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE7_SET(x)        (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE7_LSB) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE7_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE7_RESET         0
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE6_MSB           13
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE6_LSB           12
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE6_MASK          0x00003000
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE6_GET(x)        (((x) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE6_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE6_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE6_SET(x)        (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE6_LSB) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE6_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE6_RESET         0
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE5_MSB           11
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE5_LSB           10
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE5_MASK          0x00000c00
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE5_GET(x)        (((x) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE5_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE5_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE5_SET(x)        (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE5_LSB) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE5_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE5_RESET         0
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE4_MSB           9
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE4_LSB           8
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE4_MASK          0x00000300
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE4_GET(x)        (((x) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE4_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE4_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE4_SET(x)        (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE4_LSB) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE4_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE4_RESET         0
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE3_MSB           7
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE3_LSB           6
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE3_MASK          0x000000c0
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE3_GET(x)        (((x) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE3_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE3_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE3_SET(x)        (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE3_LSB) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE3_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE3_RESET         0
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE2_MSB           5
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE2_LSB           4
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE2_MASK          0x00000030
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE2_GET(x)        (((x) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE2_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE2_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE2_SET(x)        (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE2_LSB) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE2_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE2_RESET         0
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE1_MSB           3
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE1_LSB           2
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE1_MASK          0x0000000c
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE1_GET(x)        (((x) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE1_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE1_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE1_SET(x)        (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE1_LSB) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE1_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE1_RESET         0
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE0_MSB           1
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE0_LSB           0
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE0_MASK          0x00000003
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE0_GET(x)        (((x) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE0_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE0_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE0_SET(x)        (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE0_LSB) & HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE0_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_1_BKOF_SW_INT_TYPE0_RESET         0
#define HWSCH_MTU_INTERRUPT_STATUS_1_ADDRESS                         0x000090
#define HWSCH_MTU_INTERRUPT_STATUS_1_HW_MASK                         0xffffffff
#define HWSCH_MTU_INTERRUPT_STATUS_1_SW_MASK                         0xffffffff
#define HWSCH_MTU_INTERRUPT_STATUS_1_RSTMASK                         0x00000000
#define HWSCH_MTU_INTERRUPT_STATUS_1_RESET                           0x00000000

// 0x0094 (HWSCH_MTU_INTERRUPT_STATUS_2)
#define HWSCH_MTU_INTERRUPT_STATUS_2_RESERVED_0_MSB                  31
#define HWSCH_MTU_INTERRUPT_STATUS_2_RESERVED_0_LSB                  15
#define HWSCH_MTU_INTERRUPT_STATUS_2_RESERVED_0_MASK                 0xffff8000
#define HWSCH_MTU_INTERRUPT_STATUS_2_RESERVED_0_GET(x)               (((x) & HWSCH_MTU_INTERRUPT_STATUS_2_RESERVED_0_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_2_RESERVED_0_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_2_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_2_RESERVED_0_LSB) & HWSCH_MTU_INTERRUPT_STATUS_2_RESERVED_0_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_2_RESERVED_0_RESET                0
#define HWSCH_MTU_INTERRUPT_STATUS_2_TXP_SIFS_DELAY_CNT_FORINNAV_MSB 14
#define HWSCH_MTU_INTERRUPT_STATUS_2_TXP_SIFS_DELAY_CNT_FORINNAV_LSB 0
#define HWSCH_MTU_INTERRUPT_STATUS_2_TXP_SIFS_DELAY_CNT_FORINNAV_MASK 0x00007fff
#define HWSCH_MTU_INTERRUPT_STATUS_2_TXP_SIFS_DELAY_CNT_FORINNAV_GET(x) (((x) & HWSCH_MTU_INTERRUPT_STATUS_2_TXP_SIFS_DELAY_CNT_FORINNAV_MASK) >> HWSCH_MTU_INTERRUPT_STATUS_2_TXP_SIFS_DELAY_CNT_FORINNAV_LSB)
#define HWSCH_MTU_INTERRUPT_STATUS_2_TXP_SIFS_DELAY_CNT_FORINNAV_SET(x) (((0x0 | (x)) << HWSCH_MTU_INTERRUPT_STATUS_2_TXP_SIFS_DELAY_CNT_FORINNAV_LSB) & HWSCH_MTU_INTERRUPT_STATUS_2_TXP_SIFS_DELAY_CNT_FORINNAV_MASK)
#define HWSCH_MTU_INTERRUPT_STATUS_2_TXP_SIFS_DELAY_CNT_FORINNAV_RESET 0
#define HWSCH_MTU_INTERRUPT_STATUS_2_ADDRESS                         0x000094
#define HWSCH_MTU_INTERRUPT_STATUS_2_HW_MASK                         0xffffffff
#define HWSCH_MTU_INTERRUPT_STATUS_2_SW_MASK                         0xffffffff
#define HWSCH_MTU_INTERRUPT_STATUS_2_RSTMASK                         0x00000000
#define HWSCH_MTU_INTERRUPT_STATUS_2_RESET                           0x00000000

// 0x0098 (HWSCH_CCA_COUNTER0)
#define HWSCH_CCA_COUNTER0_CCA_COUNTER0_MSB                          31
#define HWSCH_CCA_COUNTER0_CCA_COUNTER0_LSB                          0
#define HWSCH_CCA_COUNTER0_CCA_COUNTER0_MASK                         0xffffffff
#define HWSCH_CCA_COUNTER0_CCA_COUNTER0_GET(x)                       (((x) & HWSCH_CCA_COUNTER0_CCA_COUNTER0_MASK) >> HWSCH_CCA_COUNTER0_CCA_COUNTER0_LSB)
#define HWSCH_CCA_COUNTER0_CCA_COUNTER0_SET(x)                       (((0x0 | (x)) << HWSCH_CCA_COUNTER0_CCA_COUNTER0_LSB) & HWSCH_CCA_COUNTER0_CCA_COUNTER0_MASK)
#define HWSCH_CCA_COUNTER0_CCA_COUNTER0_RESET                        0
#define HWSCH_CCA_COUNTER0_ADDRESS                                   0x000098
#define HWSCH_CCA_COUNTER0_HW_MASK                                   0xffffffff
#define HWSCH_CCA_COUNTER0_SW_MASK                                   0xffffffff
#define HWSCH_CCA_COUNTER0_RSTMASK                                   0x00000000
#define HWSCH_CCA_COUNTER0_RESET                                     0x00000000

// 0x009c (HWSCH_CCA_COUNTER1)
#define HWSCH_CCA_COUNTER1_CCA_COUNTER1_MSB                          31
#define HWSCH_CCA_COUNTER1_CCA_COUNTER1_LSB                          0
#define HWSCH_CCA_COUNTER1_CCA_COUNTER1_MASK                         0xffffffff
#define HWSCH_CCA_COUNTER1_CCA_COUNTER1_GET(x)                       (((x) & HWSCH_CCA_COUNTER1_CCA_COUNTER1_MASK) >> HWSCH_CCA_COUNTER1_CCA_COUNTER1_LSB)
#define HWSCH_CCA_COUNTER1_CCA_COUNTER1_SET(x)                       (((0x0 | (x)) << HWSCH_CCA_COUNTER1_CCA_COUNTER1_LSB) & HWSCH_CCA_COUNTER1_CCA_COUNTER1_MASK)
#define HWSCH_CCA_COUNTER1_CCA_COUNTER1_RESET                        0
#define HWSCH_CCA_COUNTER1_ADDRESS                                   0x00009c
#define HWSCH_CCA_COUNTER1_HW_MASK                                   0xffffffff
#define HWSCH_CCA_COUNTER1_SW_MASK                                   0xffffffff
#define HWSCH_CCA_COUNTER1_RSTMASK                                   0x00000000
#define HWSCH_CCA_COUNTER1_RESET                                     0x00000000

// 0x00a0 (HWSCH_CCA_COUNTER2)
#define HWSCH_CCA_COUNTER2_CCA_COUNTER2_MSB                          31
#define HWSCH_CCA_COUNTER2_CCA_COUNTER2_LSB                          0
#define HWSCH_CCA_COUNTER2_CCA_COUNTER2_MASK                         0xffffffff
#define HWSCH_CCA_COUNTER2_CCA_COUNTER2_GET(x)                       (((x) & HWSCH_CCA_COUNTER2_CCA_COUNTER2_MASK) >> HWSCH_CCA_COUNTER2_CCA_COUNTER2_LSB)
#define HWSCH_CCA_COUNTER2_CCA_COUNTER2_SET(x)                       (((0x0 | (x)) << HWSCH_CCA_COUNTER2_CCA_COUNTER2_LSB) & HWSCH_CCA_COUNTER2_CCA_COUNTER2_MASK)
#define HWSCH_CCA_COUNTER2_CCA_COUNTER2_RESET                        0
#define HWSCH_CCA_COUNTER2_ADDRESS                                   0x0000a0
#define HWSCH_CCA_COUNTER2_HW_MASK                                   0xffffffff
#define HWSCH_CCA_COUNTER2_SW_MASK                                   0xffffffff
#define HWSCH_CCA_COUNTER2_RSTMASK                                   0x00000000
#define HWSCH_CCA_COUNTER2_RESET                                     0x00000000

// 0x00a4 (HWSCH_CCA_CONTROL_REG)
#define HWSCH_CCA_CONTROL_REG_RESERVED_0_MSB                         31
#define HWSCH_CCA_CONTROL_REG_RESERVED_0_LSB                         16
#define HWSCH_CCA_CONTROL_REG_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CCA_CONTROL_REG_RESERVED_0_GET(x)                      (((x) & HWSCH_CCA_CONTROL_REG_RESERVED_0_MASK) >> HWSCH_CCA_CONTROL_REG_RESERVED_0_LSB)
#define HWSCH_CCA_CONTROL_REG_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_RESERVED_0_LSB) & HWSCH_CCA_CONTROL_REG_RESERVED_0_MASK)
#define HWSCH_CCA_CONTROL_REG_RESERVED_0_RESET                       0
#define HWSCH_CCA_CONTROL_REG_SW_MTU_RAW_CCA_SEL_MSB                 15
#define HWSCH_CCA_CONTROL_REG_SW_MTU_RAW_CCA_SEL_LSB                 0
#define HWSCH_CCA_CONTROL_REG_SW_MTU_RAW_CCA_SEL_MASK                0x0000ffff
#define HWSCH_CCA_CONTROL_REG_SW_MTU_RAW_CCA_SEL_GET(x)              (((x) & HWSCH_CCA_CONTROL_REG_SW_MTU_RAW_CCA_SEL_MASK) >> HWSCH_CCA_CONTROL_REG_SW_MTU_RAW_CCA_SEL_LSB)
#define HWSCH_CCA_CONTROL_REG_SW_MTU_RAW_CCA_SEL_SET(x)              (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_SW_MTU_RAW_CCA_SEL_LSB) & HWSCH_CCA_CONTROL_REG_SW_MTU_RAW_CCA_SEL_MASK)
#define HWSCH_CCA_CONTROL_REG_SW_MTU_RAW_CCA_SEL_RESET               0
#define HWSCH_CCA_CONTROL_REG_ADDRESS                                0x0000a4
#define HWSCH_CCA_CONTROL_REG_HW_MASK                                0xffffffff
#define HWSCH_CCA_CONTROL_REG_SW_MASK                                0xffffffff
#define HWSCH_CCA_CONTROL_REG_RSTMASK                                0x00000000
#define HWSCH_CCA_CONTROL_REG_RESET                                  0x00000000

// 0x00a8 (HWSCH_CCA_CONTROL_REG_1)
#define HWSCH_CCA_CONTROL_REG_1_RESERVED_0_MSB                       31
#define HWSCH_CCA_CONTROL_REG_1_RESERVED_0_LSB                       22
#define HWSCH_CCA_CONTROL_REG_1_RESERVED_0_MASK                      0xffc00000
#define HWSCH_CCA_CONTROL_REG_1_RESERVED_0_GET(x)                    (((x) & HWSCH_CCA_CONTROL_REG_1_RESERVED_0_MASK) >> HWSCH_CCA_CONTROL_REG_1_RESERVED_0_LSB)
#define HWSCH_CCA_CONTROL_REG_1_RESERVED_0_SET(x)                    (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_1_RESERVED_0_LSB) & HWSCH_CCA_CONTROL_REG_1_RESERVED_0_MASK)
#define HWSCH_CCA_CONTROL_REG_1_RESERVED_0_RESET                     0
#define HWSCH_CCA_CONTROL_REG_1_CONSIDER_RX_CCA_ONLY_MSB             21
#define HWSCH_CCA_CONTROL_REG_1_CONSIDER_RX_CCA_ONLY_LSB             21
#define HWSCH_CCA_CONTROL_REG_1_CONSIDER_RX_CCA_ONLY_MASK            0x00200000
#define HWSCH_CCA_CONTROL_REG_1_CONSIDER_RX_CCA_ONLY_GET(x)          (((x) & HWSCH_CCA_CONTROL_REG_1_CONSIDER_RX_CCA_ONLY_MASK) >> HWSCH_CCA_CONTROL_REG_1_CONSIDER_RX_CCA_ONLY_LSB)
#define HWSCH_CCA_CONTROL_REG_1_CONSIDER_RX_CCA_ONLY_SET(x)          (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_1_CONSIDER_RX_CCA_ONLY_LSB) & HWSCH_CCA_CONTROL_REG_1_CONSIDER_RX_CCA_ONLY_MASK)
#define HWSCH_CCA_CONTROL_REG_1_CONSIDER_RX_CCA_ONLY_RESET           0
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT2_SEL_MSB                   20
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT2_SEL_LSB                   18
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT2_SEL_MASK                  0x001c0000
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT2_SEL_GET(x)                (((x) & HWSCH_CCA_CONTROL_REG_1_CCA_COUNT2_SEL_MASK) >> HWSCH_CCA_CONTROL_REG_1_CCA_COUNT2_SEL_LSB)
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT2_SEL_SET(x)                (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_1_CCA_COUNT2_SEL_LSB) & HWSCH_CCA_CONTROL_REG_1_CCA_COUNT2_SEL_MASK)
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT2_SEL_RESET                 0
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT1_SEL_MSB                   17
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT1_SEL_LSB                   15
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT1_SEL_MASK                  0x00038000
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT1_SEL_GET(x)                (((x) & HWSCH_CCA_CONTROL_REG_1_CCA_COUNT1_SEL_MASK) >> HWSCH_CCA_CONTROL_REG_1_CCA_COUNT1_SEL_LSB)
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT1_SEL_SET(x)                (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_1_CCA_COUNT1_SEL_LSB) & HWSCH_CCA_CONTROL_REG_1_CCA_COUNT1_SEL_MASK)
#define HWSCH_CCA_CONTROL_REG_1_CCA_COUNT1_SEL_RESET                 0
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_BKOF_GOTO_IDLE_MSB            14
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_BKOF_GOTO_IDLE_LSB            14
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_BKOF_GOTO_IDLE_MASK           0x00004000
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_BKOF_GOTO_IDLE_GET(x)         (((x) & HWSCH_CCA_CONTROL_REG_1_SW_MTU_BKOF_GOTO_IDLE_MASK) >> HWSCH_CCA_CONTROL_REG_1_SW_MTU_BKOF_GOTO_IDLE_LSB)
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_BKOF_GOTO_IDLE_SET(x)         (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_1_SW_MTU_BKOF_GOTO_IDLE_LSB) & HWSCH_CCA_CONTROL_REG_1_SW_MTU_BKOF_GOTO_IDLE_MASK)
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_BKOF_GOTO_IDLE_RESET          0
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_CCA_FLAG_MSB                  13
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_CCA_FLAG_LSB                  13
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_CCA_FLAG_MASK                 0x00002000
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_CCA_FLAG_GET(x)               (((x) & HWSCH_CCA_CONTROL_REG_1_SW_MTU_CCA_FLAG_MASK) >> HWSCH_CCA_CONTROL_REG_1_SW_MTU_CCA_FLAG_LSB)
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_CCA_FLAG_SET(x)               (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_1_SW_MTU_CCA_FLAG_LSB) & HWSCH_CCA_CONTROL_REG_1_SW_MTU_CCA_FLAG_MASK)
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_CCA_FLAG_RESET                0
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_FINAL_CCA_SEL_MSB        12
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_FINAL_CCA_SEL_LSB        11
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_FINAL_CCA_SEL_MASK       0x00001800
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_FINAL_CCA_SEL_GET(x)     (((x) & HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_FINAL_CCA_SEL_MASK) >> HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_FINAL_CCA_SEL_LSB)
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_FINAL_CCA_SEL_SET(x)     (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_FINAL_CCA_SEL_LSB) & HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_FINAL_CCA_SEL_MASK)
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_FINAL_CCA_SEL_RESET      0
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_RAW_CCA_SEL_MSB          10
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_RAW_CCA_SEL_LSB          8
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_RAW_CCA_SEL_MASK         0x00000700
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_RAW_CCA_SEL_GET(x)       (((x) & HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_RAW_CCA_SEL_MASK) >> HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_RAW_CCA_SEL_LSB)
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_RAW_CCA_SEL_SET(x)       (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_RAW_CCA_SEL_LSB) & HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_RAW_CCA_SEL_MASK)
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_PIFS_RAW_CCA_SEL_RESET        0
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_EIFS_CCA_SEL_MSB              7
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_EIFS_CCA_SEL_LSB              0
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_EIFS_CCA_SEL_MASK             0x000000ff
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_EIFS_CCA_SEL_GET(x)           (((x) & HWSCH_CCA_CONTROL_REG_1_SW_MTU_EIFS_CCA_SEL_MASK) >> HWSCH_CCA_CONTROL_REG_1_SW_MTU_EIFS_CCA_SEL_LSB)
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_EIFS_CCA_SEL_SET(x)           (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_1_SW_MTU_EIFS_CCA_SEL_LSB) & HWSCH_CCA_CONTROL_REG_1_SW_MTU_EIFS_CCA_SEL_MASK)
#define HWSCH_CCA_CONTROL_REG_1_SW_MTU_EIFS_CCA_SEL_RESET            0
#define HWSCH_CCA_CONTROL_REG_1_ADDRESS                              0x0000a8
#define HWSCH_CCA_CONTROL_REG_1_HW_MASK                              0xffffffff
#define HWSCH_CCA_CONTROL_REG_1_SW_MASK                              0xffffffff
#define HWSCH_CCA_CONTROL_REG_1_RSTMASK                              0x00000000
#define HWSCH_CCA_CONTROL_REG_1_RESET                                0x00000000

// 0x00ac (HWSCH_CCA_CONTROL_REG_2)
#define HWSCH_CCA_CONTROL_REG_2_RESERVED_0_MSB                       31
#define HWSCH_CCA_CONTROL_REG_2_RESERVED_0_LSB                       27
#define HWSCH_CCA_CONTROL_REG_2_RESERVED_0_MASK                      0xf8000000
#define HWSCH_CCA_CONTROL_REG_2_RESERVED_0_GET(x)                    (((x) & HWSCH_CCA_CONTROL_REG_2_RESERVED_0_MASK) >> HWSCH_CCA_CONTROL_REG_2_RESERVED_0_LSB)
#define HWSCH_CCA_CONTROL_REG_2_RESERVED_0_SET(x)                    (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_2_RESERVED_0_LSB) & HWSCH_CCA_CONTROL_REG_2_RESERVED_0_MASK)
#define HWSCH_CCA_CONTROL_REG_2_RESERVED_0_RESET                     0
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_QUATERNARY_CCA_LIMIT_MSB      26
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_QUATERNARY_CCA_LIMIT_LSB      18
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_QUATERNARY_CCA_LIMIT_MASK     0x07fc0000
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_QUATERNARY_CCA_LIMIT_GET(x)   (((x) & HWSCH_CCA_CONTROL_REG_2_SW_MTU_QUATERNARY_CCA_LIMIT_MASK) >> HWSCH_CCA_CONTROL_REG_2_SW_MTU_QUATERNARY_CCA_LIMIT_LSB)
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_QUATERNARY_CCA_LIMIT_SET(x)   (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_2_SW_MTU_QUATERNARY_CCA_LIMIT_LSB) & HWSCH_CCA_CONTROL_REG_2_SW_MTU_QUATERNARY_CCA_LIMIT_MASK)
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_QUATERNARY_CCA_LIMIT_RESET    25
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_TERTIARY_CCA_LIMIT_MSB        17
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_TERTIARY_CCA_LIMIT_LSB        9
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_TERTIARY_CCA_LIMIT_MASK       0x0003fe00
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_TERTIARY_CCA_LIMIT_GET(x)     (((x) & HWSCH_CCA_CONTROL_REG_2_SW_MTU_TERTIARY_CCA_LIMIT_MASK) >> HWSCH_CCA_CONTROL_REG_2_SW_MTU_TERTIARY_CCA_LIMIT_LSB)
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_TERTIARY_CCA_LIMIT_SET(x)     (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_2_SW_MTU_TERTIARY_CCA_LIMIT_LSB) & HWSCH_CCA_CONTROL_REG_2_SW_MTU_TERTIARY_CCA_LIMIT_MASK)
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_TERTIARY_CCA_LIMIT_RESET      25
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_SECONDARY_CCA_LIMIT_MSB       8
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_SECONDARY_CCA_LIMIT_LSB       0
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_SECONDARY_CCA_LIMIT_MASK      0x000001ff
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_SECONDARY_CCA_LIMIT_GET(x)    (((x) & HWSCH_CCA_CONTROL_REG_2_SW_MTU_SECONDARY_CCA_LIMIT_MASK) >> HWSCH_CCA_CONTROL_REG_2_SW_MTU_SECONDARY_CCA_LIMIT_LSB)
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_SECONDARY_CCA_LIMIT_SET(x)    (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_2_SW_MTU_SECONDARY_CCA_LIMIT_LSB) & HWSCH_CCA_CONTROL_REG_2_SW_MTU_SECONDARY_CCA_LIMIT_MASK)
#define HWSCH_CCA_CONTROL_REG_2_SW_MTU_SECONDARY_CCA_LIMIT_RESET     25
#define HWSCH_CCA_CONTROL_REG_2_ADDRESS                              0x0000ac
#define HWSCH_CCA_CONTROL_REG_2_HW_MASK                              0xffffffff
#define HWSCH_CCA_CONTROL_REG_2_SW_MASK                              0xffffffff
#define HWSCH_CCA_CONTROL_REG_2_RSTMASK                              0x07ffffff
#define HWSCH_CCA_CONTROL_REG_2_RESET                                0x00643219

// 0x00b0 (HWSCH_CCA_CONTROL_REG_3)
#define HWSCH_CCA_CONTROL_REG_3_RESERVED_0_MSB                       31
#define HWSCH_CCA_CONTROL_REG_3_RESERVED_0_LSB                       8
#define HWSCH_CCA_CONTROL_REG_3_RESERVED_0_MASK                      0xffffff00
#define HWSCH_CCA_CONTROL_REG_3_RESERVED_0_GET(x)                    (((x) & HWSCH_CCA_CONTROL_REG_3_RESERVED_0_MASK) >> HWSCH_CCA_CONTROL_REG_3_RESERVED_0_LSB)
#define HWSCH_CCA_CONTROL_REG_3_RESERVED_0_SET(x)                    (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_3_RESERVED_0_LSB) & HWSCH_CCA_CONTROL_REG_3_RESERVED_0_MASK)
#define HWSCH_CCA_CONTROL_REG_3_RESERVED_0_RESET                     0
#define HWSCH_CCA_CONTROL_REG_3_SW_MTU_RAW_CCA_SEL_NEW_MSB           7
#define HWSCH_CCA_CONTROL_REG_3_SW_MTU_RAW_CCA_SEL_NEW_LSB           0
#define HWSCH_CCA_CONTROL_REG_3_SW_MTU_RAW_CCA_SEL_NEW_MASK          0x000000ff
#define HWSCH_CCA_CONTROL_REG_3_SW_MTU_RAW_CCA_SEL_NEW_GET(x)        (((x) & HWSCH_CCA_CONTROL_REG_3_SW_MTU_RAW_CCA_SEL_NEW_MASK) >> HWSCH_CCA_CONTROL_REG_3_SW_MTU_RAW_CCA_SEL_NEW_LSB)
#define HWSCH_CCA_CONTROL_REG_3_SW_MTU_RAW_CCA_SEL_NEW_SET(x)        (((0x0 | (x)) << HWSCH_CCA_CONTROL_REG_3_SW_MTU_RAW_CCA_SEL_NEW_LSB) & HWSCH_CCA_CONTROL_REG_3_SW_MTU_RAW_CCA_SEL_NEW_MASK)
#define HWSCH_CCA_CONTROL_REG_3_SW_MTU_RAW_CCA_SEL_NEW_RESET         0
#define HWSCH_CCA_CONTROL_REG_3_ADDRESS                              0x0000b0
#define HWSCH_CCA_CONTROL_REG_3_HW_MASK                              0xffffffff
#define HWSCH_CCA_CONTROL_REG_3_SW_MASK                              0xffffffff
#define HWSCH_CCA_CONTROL_REG_3_RSTMASK                              0x00000000
#define HWSCH_CCA_CONTROL_REG_3_RESET                                0x00000000

// 0x00b4 (HWSCH_CCA_FINAL_CONTROL_REG)
#define HWSCH_CCA_FINAL_CONTROL_REG_RESERVED_0_MSB                   31
#define HWSCH_CCA_FINAL_CONTROL_REG_RESERVED_0_LSB                   16
#define HWSCH_CCA_FINAL_CONTROL_REG_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CCA_FINAL_CONTROL_REG_RESERVED_0_GET(x)                (((x) & HWSCH_CCA_FINAL_CONTROL_REG_RESERVED_0_MASK) >> HWSCH_CCA_FINAL_CONTROL_REG_RESERVED_0_LSB)
#define HWSCH_CCA_FINAL_CONTROL_REG_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CCA_FINAL_CONTROL_REG_RESERVED_0_LSB) & HWSCH_CCA_FINAL_CONTROL_REG_RESERVED_0_MASK)
#define HWSCH_CCA_FINAL_CONTROL_REG_RESERVED_0_RESET                 0
#define HWSCH_CCA_FINAL_CONTROL_REG_SW_MTU_FINAL_CCA_SEL_MSB         15
#define HWSCH_CCA_FINAL_CONTROL_REG_SW_MTU_FINAL_CCA_SEL_LSB         0
#define HWSCH_CCA_FINAL_CONTROL_REG_SW_MTU_FINAL_CCA_SEL_MASK        0x0000ffff
#define HWSCH_CCA_FINAL_CONTROL_REG_SW_MTU_FINAL_CCA_SEL_GET(x)      (((x) & HWSCH_CCA_FINAL_CONTROL_REG_SW_MTU_FINAL_CCA_SEL_MASK) >> HWSCH_CCA_FINAL_CONTROL_REG_SW_MTU_FINAL_CCA_SEL_LSB)
#define HWSCH_CCA_FINAL_CONTROL_REG_SW_MTU_FINAL_CCA_SEL_SET(x)      (((0x0 | (x)) << HWSCH_CCA_FINAL_CONTROL_REG_SW_MTU_FINAL_CCA_SEL_LSB) & HWSCH_CCA_FINAL_CONTROL_REG_SW_MTU_FINAL_CCA_SEL_MASK)
#define HWSCH_CCA_FINAL_CONTROL_REG_SW_MTU_FINAL_CCA_SEL_RESET       0
#define HWSCH_CCA_FINAL_CONTROL_REG_ADDRESS                          0x0000b4
#define HWSCH_CCA_FINAL_CONTROL_REG_HW_MASK                          0xffffffff
#define HWSCH_CCA_FINAL_CONTROL_REG_SW_MASK                          0xffffffff
#define HWSCH_CCA_FINAL_CONTROL_REG_RSTMASK                          0x00000000
#define HWSCH_CCA_FINAL_CONTROL_REG_RESET                            0x00000000

// 0x00b8 (HWSCH_EARLY_INTERRUPT_LIMITS)
#define HWSCH_EARLY_INTERRUPT_LIMITS_RESERVED_0_MSB                  31
#define HWSCH_EARLY_INTERRUPT_LIMITS_RESERVED_0_LSB                  22
#define HWSCH_EARLY_INTERRUPT_LIMITS_RESERVED_0_MASK                 0xffc00000
#define HWSCH_EARLY_INTERRUPT_LIMITS_RESERVED_0_GET(x)               (((x) & HWSCH_EARLY_INTERRUPT_LIMITS_RESERVED_0_MASK) >> HWSCH_EARLY_INTERRUPT_LIMITS_RESERVED_0_LSB)
#define HWSCH_EARLY_INTERRUPT_LIMITS_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_EARLY_INTERRUPT_LIMITS_RESERVED_0_LSB) & HWSCH_EARLY_INTERRUPT_LIMITS_RESERVED_0_MASK)
#define HWSCH_EARLY_INTERRUPT_LIMITS_RESERVED_0_RESET                0
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_TXP_SIFS_WIDTH_LIMIT_MSB 21
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_TXP_SIFS_WIDTH_LIMIT_LSB 16
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_TXP_SIFS_WIDTH_LIMIT_MASK 0x003f0000
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_TXP_SIFS_WIDTH_LIMIT_GET(x) (((x) & HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_TXP_SIFS_WIDTH_LIMIT_MASK) >> HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_TXP_SIFS_WIDTH_LIMIT_LSB)
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_TXP_SIFS_WIDTH_LIMIT_SET(x) (((0x0 | (x)) << HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_TXP_SIFS_WIDTH_LIMIT_LSB) & HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_TXP_SIFS_WIDTH_LIMIT_MASK)
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_TXP_SIFS_WIDTH_LIMIT_RESET 5
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_CLKS_MSB 15
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_CLKS_LSB 8
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_CLKS_MASK 0x0000ff00
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_CLKS_GET(x) (((x) & HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_CLKS_MASK) >> HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_CLKS_LSB)
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_CLKS_SET(x) (((0x0 | (x)) << HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_CLKS_LSB) & HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_CLKS_MASK)
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_CLKS_RESET 1
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_US_MSB 7
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_US_LSB 0
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_US_MASK 0x000000ff
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_US_GET(x) (((x) & HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_US_MASK) >> HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_US_LSB)
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_US_SET(x) (((0x0 | (x)) << HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_US_LSB) & HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_US_MASK)
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MTU_EARLY_SW_INT_LIMIT_US_RESET 4
#define HWSCH_EARLY_INTERRUPT_LIMITS_ADDRESS                         0x0000b8
#define HWSCH_EARLY_INTERRUPT_LIMITS_HW_MASK                         0xffffffff
#define HWSCH_EARLY_INTERRUPT_LIMITS_SW_MASK                         0xffffffff
#define HWSCH_EARLY_INTERRUPT_LIMITS_RSTMASK                         0x003fffff
#define HWSCH_EARLY_INTERRUPT_LIMITS_RESET                           0x00050104

// 0x00bc (HWSCH_MTU_FOR_HMAC_CONTROLS)
#define HWSCH_MTU_FOR_HMAC_CONTROLS_RESERVED_0_MSB                   31
#define HWSCH_MTU_FOR_HMAC_CONTROLS_RESERVED_0_LSB                   8
#define HWSCH_MTU_FOR_HMAC_CONTROLS_RESERVED_0_MASK                  0xffffff00
#define HWSCH_MTU_FOR_HMAC_CONTROLS_RESERVED_0_GET(x)                (((x) & HWSCH_MTU_FOR_HMAC_CONTROLS_RESERVED_0_MASK) >> HWSCH_MTU_FOR_HMAC_CONTROLS_RESERVED_0_LSB)
#define HWSCH_MTU_FOR_HMAC_CONTROLS_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_MTU_FOR_HMAC_CONTROLS_RESERVED_0_LSB) & HWSCH_MTU_FOR_HMAC_CONTROLS_RESERVED_0_MASK)
#define HWSCH_MTU_FOR_HMAC_CONTROLS_RESERVED_0_RESET                 0
#define HWSCH_MTU_FOR_HMAC_CONTROLS_SW_MTU_HW_BACKOFF_VALID_MSB      7
#define HWSCH_MTU_FOR_HMAC_CONTROLS_SW_MTU_HW_BACKOFF_VALID_LSB      0
#define HWSCH_MTU_FOR_HMAC_CONTROLS_SW_MTU_HW_BACKOFF_VALID_MASK     0x000000ff
#define HWSCH_MTU_FOR_HMAC_CONTROLS_SW_MTU_HW_BACKOFF_VALID_GET(x)   (((x) & HWSCH_MTU_FOR_HMAC_CONTROLS_SW_MTU_HW_BACKOFF_VALID_MASK) >> HWSCH_MTU_FOR_HMAC_CONTROLS_SW_MTU_HW_BACKOFF_VALID_LSB)
#define HWSCH_MTU_FOR_HMAC_CONTROLS_SW_MTU_HW_BACKOFF_VALID_SET(x)   (((0x0 | (x)) << HWSCH_MTU_FOR_HMAC_CONTROLS_SW_MTU_HW_BACKOFF_VALID_LSB) & HWSCH_MTU_FOR_HMAC_CONTROLS_SW_MTU_HW_BACKOFF_VALID_MASK)
#define HWSCH_MTU_FOR_HMAC_CONTROLS_SW_MTU_HW_BACKOFF_VALID_RESET    255
#define HWSCH_MTU_FOR_HMAC_CONTROLS_ADDRESS                          0x0000bc
#define HWSCH_MTU_FOR_HMAC_CONTROLS_HW_MASK                          0xffffffff
#define HWSCH_MTU_FOR_HMAC_CONTROLS_SW_MASK                          0xffffffff
#define HWSCH_MTU_FOR_HMAC_CONTROLS_RSTMASK                          0x000000ff
#define HWSCH_MTU_FOR_HMAC_CONTROLS_RESET                            0x000000ff

// 0x00c0 (HWSCH_LFSR_DATA_1_0)
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_1_MSB                          31
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_1_LSB                          16
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_1_MASK                         0xffff0000
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_1_GET(x)                       (((x) & HWSCH_LFSR_DATA_1_0_LFSR_DATA_1_MASK) >> HWSCH_LFSR_DATA_1_0_LFSR_DATA_1_LSB)
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_1_SET(x)                       (((0x0 | (x)) << HWSCH_LFSR_DATA_1_0_LFSR_DATA_1_LSB) & HWSCH_LFSR_DATA_1_0_LFSR_DATA_1_MASK)
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_1_RESET                        0
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_0_MSB                          15
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_0_LSB                          0
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_0_MASK                         0x0000ffff
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_0_GET(x)                       (((x) & HWSCH_LFSR_DATA_1_0_LFSR_DATA_0_MASK) >> HWSCH_LFSR_DATA_1_0_LFSR_DATA_0_LSB)
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_0_SET(x)                       (((0x0 | (x)) << HWSCH_LFSR_DATA_1_0_LFSR_DATA_0_LSB) & HWSCH_LFSR_DATA_1_0_LFSR_DATA_0_MASK)
#define HWSCH_LFSR_DATA_1_0_LFSR_DATA_0_RESET                        0
#define HWSCH_LFSR_DATA_1_0_ADDRESS                                  0x0000c0
#define HWSCH_LFSR_DATA_1_0_HW_MASK                                  0xffffffff
#define HWSCH_LFSR_DATA_1_0_SW_MASK                                  0xffffffff
#define HWSCH_LFSR_DATA_1_0_RSTMASK                                  0x00000000
#define HWSCH_LFSR_DATA_1_0_RESET                                    0x00000000

// 0x00c4 (HWSCH_LFSR_DATA_3_2)
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_3_MSB                          31
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_3_LSB                          16
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_3_MASK                         0xffff0000
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_3_GET(x)                       (((x) & HWSCH_LFSR_DATA_3_2_LFSR_DATA_3_MASK) >> HWSCH_LFSR_DATA_3_2_LFSR_DATA_3_LSB)
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_3_SET(x)                       (((0x0 | (x)) << HWSCH_LFSR_DATA_3_2_LFSR_DATA_3_LSB) & HWSCH_LFSR_DATA_3_2_LFSR_DATA_3_MASK)
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_3_RESET                        0
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_2_MSB                          15
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_2_LSB                          0
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_2_MASK                         0x0000ffff
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_2_GET(x)                       (((x) & HWSCH_LFSR_DATA_3_2_LFSR_DATA_2_MASK) >> HWSCH_LFSR_DATA_3_2_LFSR_DATA_2_LSB)
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_2_SET(x)                       (((0x0 | (x)) << HWSCH_LFSR_DATA_3_2_LFSR_DATA_2_LSB) & HWSCH_LFSR_DATA_3_2_LFSR_DATA_2_MASK)
#define HWSCH_LFSR_DATA_3_2_LFSR_DATA_2_RESET                        0
#define HWSCH_LFSR_DATA_3_2_ADDRESS                                  0x0000c4
#define HWSCH_LFSR_DATA_3_2_HW_MASK                                  0xffffffff
#define HWSCH_LFSR_DATA_3_2_SW_MASK                                  0xffffffff
#define HWSCH_LFSR_DATA_3_2_RSTMASK                                  0x00000000
#define HWSCH_LFSR_DATA_3_2_RESET                                    0x00000000

// 0x00c8 (HWSCH_LFSR_DATA_5_4)
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_5_MSB                          31
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_5_LSB                          16
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_5_MASK                         0xffff0000
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_5_GET(x)                       (((x) & HWSCH_LFSR_DATA_5_4_LFSR_DATA_5_MASK) >> HWSCH_LFSR_DATA_5_4_LFSR_DATA_5_LSB)
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_5_SET(x)                       (((0x0 | (x)) << HWSCH_LFSR_DATA_5_4_LFSR_DATA_5_LSB) & HWSCH_LFSR_DATA_5_4_LFSR_DATA_5_MASK)
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_5_RESET                        0
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_4_MSB                          15
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_4_LSB                          0
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_4_MASK                         0x0000ffff
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_4_GET(x)                       (((x) & HWSCH_LFSR_DATA_5_4_LFSR_DATA_4_MASK) >> HWSCH_LFSR_DATA_5_4_LFSR_DATA_4_LSB)
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_4_SET(x)                       (((0x0 | (x)) << HWSCH_LFSR_DATA_5_4_LFSR_DATA_4_LSB) & HWSCH_LFSR_DATA_5_4_LFSR_DATA_4_MASK)
#define HWSCH_LFSR_DATA_5_4_LFSR_DATA_4_RESET                        0
#define HWSCH_LFSR_DATA_5_4_ADDRESS                                  0x0000c8
#define HWSCH_LFSR_DATA_5_4_HW_MASK                                  0xffffffff
#define HWSCH_LFSR_DATA_5_4_SW_MASK                                  0xffffffff
#define HWSCH_LFSR_DATA_5_4_RSTMASK                                  0x00000000
#define HWSCH_LFSR_DATA_5_4_RESET                                    0x00000000

// 0x00cc (HWSCH_LFSR_DATA_7_6)
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_7_MSB                          31
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_7_LSB                          16
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_7_MASK                         0xffff0000
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_7_GET(x)                       (((x) & HWSCH_LFSR_DATA_7_6_LFSR_DATA_7_MASK) >> HWSCH_LFSR_DATA_7_6_LFSR_DATA_7_LSB)
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_7_SET(x)                       (((0x0 | (x)) << HWSCH_LFSR_DATA_7_6_LFSR_DATA_7_LSB) & HWSCH_LFSR_DATA_7_6_LFSR_DATA_7_MASK)
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_7_RESET                        0
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_6_MSB                          15
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_6_LSB                          0
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_6_MASK                         0x0000ffff
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_6_GET(x)                       (((x) & HWSCH_LFSR_DATA_7_6_LFSR_DATA_6_MASK) >> HWSCH_LFSR_DATA_7_6_LFSR_DATA_6_LSB)
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_6_SET(x)                       (((0x0 | (x)) << HWSCH_LFSR_DATA_7_6_LFSR_DATA_6_LSB) & HWSCH_LFSR_DATA_7_6_LFSR_DATA_6_MASK)
#define HWSCH_LFSR_DATA_7_6_LFSR_DATA_6_RESET                        0
#define HWSCH_LFSR_DATA_7_6_ADDRESS                                  0x0000cc
#define HWSCH_LFSR_DATA_7_6_HW_MASK                                  0xffffffff
#define HWSCH_LFSR_DATA_7_6_SW_MASK                                  0xffffffff
#define HWSCH_LFSR_DATA_7_6_RSTMASK                                  0x00000000
#define HWSCH_LFSR_DATA_7_6_RESET                                    0x00000000

// 0x00d0 (HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0)
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_MSB 31
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_LSB 0
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_MASK 0xffffffff
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_GET(x) (((x) & HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_MASK) >> HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_LSB)
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SET(x) (((0x0 | (x)) << HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_LSB) & HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_MASK)
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_RESET 0
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_ADDRESS              0x0000d0
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_HW_MASK              0xffffffff
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_SW_MASK              0xffffffff
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_RSTMASK              0x00000000
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0_RESET                0x00000000

// 0x00d4 (HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4)
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_MSB 31
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_LSB 0
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_MASK 0xffffffff
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_GET(x) (((x) & HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_MASK) >> HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_LSB)
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SET(x) (((0x0 | (x)) << HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_LSB) & HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_MASK)
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_RESET 0
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_ADDRESS              0x0000d4
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_HW_MASK              0xffffffff
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_SW_MASK              0xffffffff
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_RSTMASK              0x00000000
#define HWSCH_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4_RESET                0x00000000

// 0x00d8 (HWSCH_ONE_SEC_LIMIT)
#define HWSCH_ONE_SEC_LIMIT_RESERVED_0_MSB                           31
#define HWSCH_ONE_SEC_LIMIT_RESERVED_0_LSB                           20
#define HWSCH_ONE_SEC_LIMIT_RESERVED_0_MASK                          0xfff00000
#define HWSCH_ONE_SEC_LIMIT_RESERVED_0_GET(x)                        (((x) & HWSCH_ONE_SEC_LIMIT_RESERVED_0_MASK) >> HWSCH_ONE_SEC_LIMIT_RESERVED_0_LSB)
#define HWSCH_ONE_SEC_LIMIT_RESERVED_0_SET(x)                        (((0x0 | (x)) << HWSCH_ONE_SEC_LIMIT_RESERVED_0_LSB) & HWSCH_ONE_SEC_LIMIT_RESERVED_0_MASK)
#define HWSCH_ONE_SEC_LIMIT_RESERVED_0_RESET                         0
#define HWSCH_ONE_SEC_LIMIT_SW_MTU_ONE_SEC_LIMIT_MSB                 19
#define HWSCH_ONE_SEC_LIMIT_SW_MTU_ONE_SEC_LIMIT_LSB                 0
#define HWSCH_ONE_SEC_LIMIT_SW_MTU_ONE_SEC_LIMIT_MASK                0x000fffff
#define HWSCH_ONE_SEC_LIMIT_SW_MTU_ONE_SEC_LIMIT_GET(x)              (((x) & HWSCH_ONE_SEC_LIMIT_SW_MTU_ONE_SEC_LIMIT_MASK) >> HWSCH_ONE_SEC_LIMIT_SW_MTU_ONE_SEC_LIMIT_LSB)
#define HWSCH_ONE_SEC_LIMIT_SW_MTU_ONE_SEC_LIMIT_SET(x)              (((0x0 | (x)) << HWSCH_ONE_SEC_LIMIT_SW_MTU_ONE_SEC_LIMIT_LSB) & HWSCH_ONE_SEC_LIMIT_SW_MTU_ONE_SEC_LIMIT_MASK)
#define HWSCH_ONE_SEC_LIMIT_SW_MTU_ONE_SEC_LIMIT_RESET               999999
#define HWSCH_ONE_SEC_LIMIT_ADDRESS                                  0x0000d8
#define HWSCH_ONE_SEC_LIMIT_HW_MASK                                  0xffffffff
#define HWSCH_ONE_SEC_LIMIT_SW_MASK                                  0xffffffff
#define HWSCH_ONE_SEC_LIMIT_RSTMASK                                  0x000fffff
#define HWSCH_ONE_SEC_LIMIT_RESET                                    0x000f423f

// 0x00dc (HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV)
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RESERVED_0_MSB              31
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RESERVED_0_LSB              15
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RESERVED_0_MASK             0xffff8000
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RESERVED_0_GET(x)           (((x) & HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RESERVED_0_MASK) >> HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RESERVED_0_LSB)
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RESERVED_0_SET(x)           (((0x0 | (x)) << HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RESERVED_0_LSB) & HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RESERVED_0_MASK)
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RESERVED_0_RESET            0
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_SW_MTU_SIFS_LIMIT_FORINNAV_MSB 14
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_SW_MTU_SIFS_LIMIT_FORINNAV_LSB 0
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_SW_MTU_SIFS_LIMIT_FORINNAV_MASK 0x00007fff
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_SW_MTU_SIFS_LIMIT_FORINNAV_GET(x) (((x) & HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_SW_MTU_SIFS_LIMIT_FORINNAV_MASK) >> HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_SW_MTU_SIFS_LIMIT_FORINNAV_LSB)
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_SW_MTU_SIFS_LIMIT_FORINNAV_SET(x) (((0x0 | (x)) << HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_SW_MTU_SIFS_LIMIT_FORINNAV_LSB) & HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_SW_MTU_SIFS_LIMIT_FORINNAV_MASK)
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_SW_MTU_SIFS_LIMIT_FORINNAV_RESET 400
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_ADDRESS                     0x0000dc
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_HW_MASK                     0xffffffff
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_SW_MASK                     0xffffffff
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RSTMASK                     0x00007fff
#define HWSCH_SW_MTU_SIFS_LIMIT_FORINNAV_RESET                       0x00000190

// 0x00e0 (HWSCH_PRIMARY_CCA_HISTOGRAM_LOW)
#define HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_PRIMARY_CCA_HISTOGRAM31TO0_MSB 31
#define HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_PRIMARY_CCA_HISTOGRAM31TO0_LSB 0
#define HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_PRIMARY_CCA_HISTOGRAM31TO0_MASK 0xffffffff
#define HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_PRIMARY_CCA_HISTOGRAM31TO0_GET(x) (((x) & HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_PRIMARY_CCA_HISTOGRAM31TO0_MASK) >> HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_PRIMARY_CCA_HISTOGRAM31TO0_LSB)
#define HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_PRIMARY_CCA_HISTOGRAM31TO0_SET(x) (((0x0 | (x)) << HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_PRIMARY_CCA_HISTOGRAM31TO0_LSB) & HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_PRIMARY_CCA_HISTOGRAM31TO0_MASK)
#define HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_PRIMARY_CCA_HISTOGRAM31TO0_RESET 4294967295
#define HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_ADDRESS                      0x0000e0
#define HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_HW_MASK                      0xffffffff
#define HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_SW_MASK                      0xffffffff
#define HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_RSTMASK                      0xffffffff
#define HWSCH_PRIMARY_CCA_HISTOGRAM_LOW_RESET                        0xffffffff

// 0x00e4 (HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH)
#define HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_PRIMARY_CCA_HISTOGRAM63TO32_MSB 31
#define HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_PRIMARY_CCA_HISTOGRAM63TO32_LSB 0
#define HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_PRIMARY_CCA_HISTOGRAM63TO32_MASK 0xffffffff
#define HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_PRIMARY_CCA_HISTOGRAM63TO32_GET(x) (((x) & HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_PRIMARY_CCA_HISTOGRAM63TO32_MASK) >> HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_PRIMARY_CCA_HISTOGRAM63TO32_LSB)
#define HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_PRIMARY_CCA_HISTOGRAM63TO32_SET(x) (((0x0 | (x)) << HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_PRIMARY_CCA_HISTOGRAM63TO32_LSB) & HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_PRIMARY_CCA_HISTOGRAM63TO32_MASK)
#define HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_PRIMARY_CCA_HISTOGRAM63TO32_RESET 4294967295
#define HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_ADDRESS                     0x0000e4
#define HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_HW_MASK                     0xffffffff
#define HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_SW_MASK                     0xffffffff
#define HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_RSTMASK                     0xffffffff
#define HWSCH_PRIMARY_CCA_HISTOGRAM_HIGH_RESET                       0xffffffff

// 0x00e8 (HWSCH_SECONDARY_CCA_HISTOGRAM_LOW)
#define HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_SECONDARY_CCA_HISTOGRAM31TO0_MSB 31
#define HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_SECONDARY_CCA_HISTOGRAM31TO0_LSB 0
#define HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_SECONDARY_CCA_HISTOGRAM31TO0_MASK 0xffffffff
#define HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_SECONDARY_CCA_HISTOGRAM31TO0_GET(x) (((x) & HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_SECONDARY_CCA_HISTOGRAM31TO0_MASK) >> HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_SECONDARY_CCA_HISTOGRAM31TO0_LSB)
#define HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_SECONDARY_CCA_HISTOGRAM31TO0_SET(x) (((0x0 | (x)) << HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_SECONDARY_CCA_HISTOGRAM31TO0_LSB) & HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_SECONDARY_CCA_HISTOGRAM31TO0_MASK)
#define HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_SECONDARY_CCA_HISTOGRAM31TO0_RESET 4294967295
#define HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_ADDRESS                    0x0000e8
#define HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_HW_MASK                    0xffffffff
#define HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_SW_MASK                    0xffffffff
#define HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_RSTMASK                    0xffffffff
#define HWSCH_SECONDARY_CCA_HISTOGRAM_LOW_RESET                      0xffffffff

// 0x00ec (HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH)
#define HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_SECONDARY_CCA_HISTOGRAM63TO32_MSB 31
#define HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_SECONDARY_CCA_HISTOGRAM63TO32_LSB 0
#define HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_SECONDARY_CCA_HISTOGRAM63TO32_MASK 0xffffffff
#define HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_SECONDARY_CCA_HISTOGRAM63TO32_GET(x) (((x) & HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_SECONDARY_CCA_HISTOGRAM63TO32_MASK) >> HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_SECONDARY_CCA_HISTOGRAM63TO32_LSB)
#define HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_SECONDARY_CCA_HISTOGRAM63TO32_SET(x) (((0x0 | (x)) << HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_SECONDARY_CCA_HISTOGRAM63TO32_LSB) & HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_SECONDARY_CCA_HISTOGRAM63TO32_MASK)
#define HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_SECONDARY_CCA_HISTOGRAM63TO32_RESET 4294967295
#define HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_ADDRESS                   0x0000ec
#define HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_HW_MASK                   0xffffffff
#define HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_SW_MASK                   0xffffffff
#define HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_RSTMASK                   0xffffffff
#define HWSCH_SECONDARY_CCA_HISTOGRAM_HIGH_RESET                     0xffffffff

// 0x00f0 (HWSCH_TERTIARY_CCA_HISTOGRAM_LOW)
#define HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_TERTIARY_CCA_HISTOGRAM31TO0_MSB 31
#define HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_TERTIARY_CCA_HISTOGRAM31TO0_LSB 0
#define HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_TERTIARY_CCA_HISTOGRAM31TO0_MASK 0xffffffff
#define HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_TERTIARY_CCA_HISTOGRAM31TO0_GET(x) (((x) & HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_TERTIARY_CCA_HISTOGRAM31TO0_MASK) >> HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_TERTIARY_CCA_HISTOGRAM31TO0_LSB)
#define HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_TERTIARY_CCA_HISTOGRAM31TO0_SET(x) (((0x0 | (x)) << HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_TERTIARY_CCA_HISTOGRAM31TO0_LSB) & HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_TERTIARY_CCA_HISTOGRAM31TO0_MASK)
#define HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_TERTIARY_CCA_HISTOGRAM31TO0_RESET 4294967295
#define HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_ADDRESS                     0x0000f0
#define HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_HW_MASK                     0xffffffff
#define HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_SW_MASK                     0xffffffff
#define HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_RSTMASK                     0xffffffff
#define HWSCH_TERTIARY_CCA_HISTOGRAM_LOW_RESET                       0xffffffff

// 0x00f4 (HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH)
#define HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_TERTIARY_CCA_HISTOGRAM63TO32_MSB 31
#define HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_TERTIARY_CCA_HISTOGRAM63TO32_LSB 0
#define HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_TERTIARY_CCA_HISTOGRAM63TO32_MASK 0xffffffff
#define HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_TERTIARY_CCA_HISTOGRAM63TO32_GET(x) (((x) & HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_TERTIARY_CCA_HISTOGRAM63TO32_MASK) >> HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_TERTIARY_CCA_HISTOGRAM63TO32_LSB)
#define HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_TERTIARY_CCA_HISTOGRAM63TO32_SET(x) (((0x0 | (x)) << HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_TERTIARY_CCA_HISTOGRAM63TO32_LSB) & HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_TERTIARY_CCA_HISTOGRAM63TO32_MASK)
#define HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_TERTIARY_CCA_HISTOGRAM63TO32_RESET 4294967295
#define HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_ADDRESS                    0x0000f4
#define HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_HW_MASK                    0xffffffff
#define HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_SW_MASK                    0xffffffff
#define HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_RSTMASK                    0xffffffff
#define HWSCH_TERTIARY_CCA_HISTOGRAM_HIGH_RESET                      0xffffffff

// 0x00f8 (HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW)
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_QUATERNARY_CCA_HISTOGRAM31TO0_MSB 31
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_QUATERNARY_CCA_HISTOGRAM31TO0_LSB 0
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_QUATERNARY_CCA_HISTOGRAM31TO0_MASK 0xffffffff
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_QUATERNARY_CCA_HISTOGRAM31TO0_GET(x) (((x) & HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_QUATERNARY_CCA_HISTOGRAM31TO0_MASK) >> HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_QUATERNARY_CCA_HISTOGRAM31TO0_LSB)
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_QUATERNARY_CCA_HISTOGRAM31TO0_SET(x) (((0x0 | (x)) << HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_QUATERNARY_CCA_HISTOGRAM31TO0_LSB) & HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_QUATERNARY_CCA_HISTOGRAM31TO0_MASK)
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_QUATERNARY_CCA_HISTOGRAM31TO0_RESET 4294967295
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_ADDRESS                   0x0000f8
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_HW_MASK                   0xffffffff
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_SW_MASK                   0xffffffff
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_RSTMASK                   0xffffffff
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_LOW_RESET                     0xffffffff

// 0x00fc (HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH)
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_QUATERNARY_CCA_HISTOGRAM63TO32_MSB 31
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_QUATERNARY_CCA_HISTOGRAM63TO32_LSB 0
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_QUATERNARY_CCA_HISTOGRAM63TO32_MASK 0xffffffff
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_QUATERNARY_CCA_HISTOGRAM63TO32_GET(x) (((x) & HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_QUATERNARY_CCA_HISTOGRAM63TO32_MASK) >> HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_QUATERNARY_CCA_HISTOGRAM63TO32_LSB)
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_QUATERNARY_CCA_HISTOGRAM63TO32_SET(x) (((0x0 | (x)) << HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_QUATERNARY_CCA_HISTOGRAM63TO32_LSB) & HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_QUATERNARY_CCA_HISTOGRAM63TO32_MASK)
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_QUATERNARY_CCA_HISTOGRAM63TO32_RESET 4294967295
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_ADDRESS                  0x0000fc
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_HW_MASK                  0xffffffff
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_SW_MASK                  0xffffffff
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_RSTMASK                  0xffffffff
#define HWSCH_QUATERNARY_CCA_HISTOGRAM_HIGH_RESET                    0xffffffff

// 0x0100 (HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK)
#define HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_SW_SECONDARY_CCA_HISTOGRAM_MASK_MSB 31
#define HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_SW_SECONDARY_CCA_HISTOGRAM_MASK_LSB 0
#define HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_SW_SECONDARY_CCA_HISTOGRAM_MASK_MASK 0xffffffff
#define HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_SW_SECONDARY_CCA_HISTOGRAM_MASK_GET(x) (((x) & HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_SW_SECONDARY_CCA_HISTOGRAM_MASK_MASK) >> HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_SW_SECONDARY_CCA_HISTOGRAM_MASK_LSB)
#define HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_SW_SECONDARY_CCA_HISTOGRAM_MASK_SET(x) (((0x0 | (x)) << HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_SW_SECONDARY_CCA_HISTOGRAM_MASK_LSB) & HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_SW_SECONDARY_CCA_HISTOGRAM_MASK_MASK)
#define HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_SW_SECONDARY_CCA_HISTOGRAM_MASK_RESET 522240
#define HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_ADDRESS                0x000100
#define HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_HW_MASK                0xffffffff
#define HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_SW_MASK                0xffffffff
#define HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_RSTMASK                0xffffffff
#define HWSCH_SW_SECONDARY_CCA_HISTOGRAM_MASK_RESET                  0x0007f800

// 0x0104 (HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK)
#define HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_SW_TERTIARY_CCA_HISTOGRAM_MASK_MSB 31
#define HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_SW_TERTIARY_CCA_HISTOGRAM_MASK_LSB 0
#define HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_SW_TERTIARY_CCA_HISTOGRAM_MASK_MASK 0xffffffff
#define HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_SW_TERTIARY_CCA_HISTOGRAM_MASK_GET(x) (((x) & HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_SW_TERTIARY_CCA_HISTOGRAM_MASK_MASK) >> HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_SW_TERTIARY_CCA_HISTOGRAM_MASK_LSB)
#define HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_SW_TERTIARY_CCA_HISTOGRAM_MASK_SET(x) (((0x0 | (x)) << HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_SW_TERTIARY_CCA_HISTOGRAM_MASK_LSB) & HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_SW_TERTIARY_CCA_HISTOGRAM_MASK_MASK)
#define HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_SW_TERTIARY_CCA_HISTOGRAM_MASK_RESET 522240
#define HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_ADDRESS                 0x000104
#define HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_HW_MASK                 0xffffffff
#define HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_SW_MASK                 0xffffffff
#define HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_RSTMASK                 0xffffffff
#define HWSCH_SW_TERTIARY_CCA_HISTOGRAM_MASK_RESET                   0x0007f800

// 0x0108 (HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK)
#define HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SW_QUATERNARY_CCA_HISTOGRAM_MASK_MSB 31
#define HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SW_QUATERNARY_CCA_HISTOGRAM_MASK_LSB 0
#define HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SW_QUATERNARY_CCA_HISTOGRAM_MASK_MASK 0xffffffff
#define HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SW_QUATERNARY_CCA_HISTOGRAM_MASK_GET(x) (((x) & HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SW_QUATERNARY_CCA_HISTOGRAM_MASK_MASK) >> HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SW_QUATERNARY_CCA_HISTOGRAM_MASK_LSB)
#define HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SET(x) (((0x0 | (x)) << HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SW_QUATERNARY_CCA_HISTOGRAM_MASK_LSB) & HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SW_QUATERNARY_CCA_HISTOGRAM_MASK_MASK)
#define HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SW_QUATERNARY_CCA_HISTOGRAM_MASK_RESET 522240
#define HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_ADDRESS               0x000108
#define HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_HW_MASK               0xffffffff
#define HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_SW_MASK               0xffffffff
#define HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_RSTMASK               0xffffffff
#define HWSCH_SW_QUATERNARY_CCA_HISTOGRAM_MASK_RESET                 0x0007f800

// 0x010c (HWSCH_SW_CCA_HISTOGRAM_MASK_MISC)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_1_MSB              31
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_1_LSB              14
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_1_MASK             0xffffc000
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_1_GET(x)           (((x) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_1_MASK) >> HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_1_LSB)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_1_SET(x)           (((0x0 | (x)) << HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_1_LSB) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_1_MASK)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_1_RESET            0
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_SAMPLING_RATE_MSB 13
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_SAMPLING_RATE_LSB 8
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_SAMPLING_RATE_MASK 0x00003f00
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_SAMPLING_RATE_GET(x) (((x) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_SAMPLING_RATE_MASK) >> HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_SAMPLING_RATE_LSB)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_SAMPLING_RATE_SET(x) (((0x0 | (x)) << HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_SAMPLING_RATE_LSB) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_SAMPLING_RATE_MASK)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_SAMPLING_RATE_RESET 3
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_0_MSB              7
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_0_LSB              7
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_0_MASK             0x00000080
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_0_GET(x)           (((x) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_0_MASK) >> HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_0_LSB)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_0_SET(x)           (((0x0 | (x)) << HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_0_LSB) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_0_MASK)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESERVED_0_RESET            0
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_NON6MBPS_MSB 6
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_NON6MBPS_LSB 6
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_NON6MBPS_MASK 0x00000040
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_NON6MBPS_GET(x) (((x) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_NON6MBPS_MASK) >> HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_NON6MBPS_LSB)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_NON6MBPS_SET(x) (((0x0 | (x)) << HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_NON6MBPS_LSB) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_NON6MBPS_MASK)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_NON6MBPS_RESET 0
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_NON6MBPS_MSB 5
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_NON6MBPS_LSB 5
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_NON6MBPS_MASK 0x00000020
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_NON6MBPS_GET(x) (((x) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_NON6MBPS_MASK) >> HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_NON6MBPS_LSB)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_NON6MBPS_SET(x) (((0x0 | (x)) << HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_NON6MBPS_LSB) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_NON6MBPS_MASK)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_NON6MBPS_RESET 0
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_6MBPS_MSB 4
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_6MBPS_LSB 4
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_6MBPS_MASK 0x00000010
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_6MBPS_GET(x) (((x) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_6MBPS_MASK) >> HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_6MBPS_LSB)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_6MBPS_SET(x) (((0x0 | (x)) << HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_6MBPS_LSB) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_6MBPS_MASK)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_80MHZ_CCA_IS_IDLE_6MBPS_RESET 0
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_6MBPS_MSB 3
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_6MBPS_LSB 3
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_6MBPS_MASK 0x00000008
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_6MBPS_GET(x) (((x) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_6MBPS_MASK) >> HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_6MBPS_LSB)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_6MBPS_SET(x) (((0x0 | (x)) << HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_6MBPS_LSB) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_6MBPS_MASK)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_MTU_TPE_40MHZ_CCA_IS_IDLE_6MBPS_RESET 0
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_MASK_SHIFT_MSB 2
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_MASK_SHIFT_LSB 0
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_MASK_SHIFT_MASK 0x00000007
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_MASK_SHIFT_GET(x) (((x) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_MASK_SHIFT_MASK) >> HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_MASK_SHIFT_LSB)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_MASK_SHIFT_SET(x) (((0x0 | (x)) << HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_MASK_SHIFT_LSB) & HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_MASK_SHIFT_MASK)
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_CCA_HISTOGRAM_MASK_SHIFT_RESET 2
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_ADDRESS                     0x00010c
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_HW_MASK                     0xffffffff
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_SW_MASK                     0xffffffff
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RSTMASK                     0x00003f07
#define HWSCH_SW_CCA_HISTOGRAM_MASK_MISC_RESET                       0x00000302

// 0x0110 (HWSCH_CCA_SECONDARY_HISTOGRAM)
#define HWSCH_CCA_SECONDARY_HISTOGRAM_CCA_SECONDARY_HISTOGRAM_MSB    31
#define HWSCH_CCA_SECONDARY_HISTOGRAM_CCA_SECONDARY_HISTOGRAM_LSB    0
#define HWSCH_CCA_SECONDARY_HISTOGRAM_CCA_SECONDARY_HISTOGRAM_MASK   0xffffffff
#define HWSCH_CCA_SECONDARY_HISTOGRAM_CCA_SECONDARY_HISTOGRAM_GET(x) (((x) & HWSCH_CCA_SECONDARY_HISTOGRAM_CCA_SECONDARY_HISTOGRAM_MASK) >> HWSCH_CCA_SECONDARY_HISTOGRAM_CCA_SECONDARY_HISTOGRAM_LSB)
#define HWSCH_CCA_SECONDARY_HISTOGRAM_CCA_SECONDARY_HISTOGRAM_SET(x) (((0x0 | (x)) << HWSCH_CCA_SECONDARY_HISTOGRAM_CCA_SECONDARY_HISTOGRAM_LSB) & HWSCH_CCA_SECONDARY_HISTOGRAM_CCA_SECONDARY_HISTOGRAM_MASK)
#define HWSCH_CCA_SECONDARY_HISTOGRAM_CCA_SECONDARY_HISTOGRAM_RESET  0
#define HWSCH_CCA_SECONDARY_HISTOGRAM_ADDRESS                        0x000110
#define HWSCH_CCA_SECONDARY_HISTOGRAM_HW_MASK                        0xffffffff
#define HWSCH_CCA_SECONDARY_HISTOGRAM_SW_MASK                        0xffffffff
#define HWSCH_CCA_SECONDARY_HISTOGRAM_RSTMASK                        0x00000000
#define HWSCH_CCA_SECONDARY_HISTOGRAM_RESET                          0x00000000

// 0x0114 (HWSCH_CCA_TERTIARY_HISTOGRAM)
#define HWSCH_CCA_TERTIARY_HISTOGRAM_CCA_TERTIARY_HISTOGRAM_MSB      31
#define HWSCH_CCA_TERTIARY_HISTOGRAM_CCA_TERTIARY_HISTOGRAM_LSB      0
#define HWSCH_CCA_TERTIARY_HISTOGRAM_CCA_TERTIARY_HISTOGRAM_MASK     0xffffffff
#define HWSCH_CCA_TERTIARY_HISTOGRAM_CCA_TERTIARY_HISTOGRAM_GET(x)   (((x) & HWSCH_CCA_TERTIARY_HISTOGRAM_CCA_TERTIARY_HISTOGRAM_MASK) >> HWSCH_CCA_TERTIARY_HISTOGRAM_CCA_TERTIARY_HISTOGRAM_LSB)
#define HWSCH_CCA_TERTIARY_HISTOGRAM_CCA_TERTIARY_HISTOGRAM_SET(x)   (((0x0 | (x)) << HWSCH_CCA_TERTIARY_HISTOGRAM_CCA_TERTIARY_HISTOGRAM_LSB) & HWSCH_CCA_TERTIARY_HISTOGRAM_CCA_TERTIARY_HISTOGRAM_MASK)
#define HWSCH_CCA_TERTIARY_HISTOGRAM_CCA_TERTIARY_HISTOGRAM_RESET    0
#define HWSCH_CCA_TERTIARY_HISTOGRAM_ADDRESS                         0x000114
#define HWSCH_CCA_TERTIARY_HISTOGRAM_HW_MASK                         0xffffffff
#define HWSCH_CCA_TERTIARY_HISTOGRAM_SW_MASK                         0xffffffff
#define HWSCH_CCA_TERTIARY_HISTOGRAM_RSTMASK                         0x00000000
#define HWSCH_CCA_TERTIARY_HISTOGRAM_RESET                           0x00000000

// 0x0118 (HWSCH_CCA_QUATERNARY_HISTOGRAM)
#define HWSCH_CCA_QUATERNARY_HISTOGRAM_CCA_QUATERNARY_HISTOGRAM_MSB  31
#define HWSCH_CCA_QUATERNARY_HISTOGRAM_CCA_QUATERNARY_HISTOGRAM_LSB  0
#define HWSCH_CCA_QUATERNARY_HISTOGRAM_CCA_QUATERNARY_HISTOGRAM_MASK 0xffffffff
#define HWSCH_CCA_QUATERNARY_HISTOGRAM_CCA_QUATERNARY_HISTOGRAM_GET(x) (((x) & HWSCH_CCA_QUATERNARY_HISTOGRAM_CCA_QUATERNARY_HISTOGRAM_MASK) >> HWSCH_CCA_QUATERNARY_HISTOGRAM_CCA_QUATERNARY_HISTOGRAM_LSB)
#define HWSCH_CCA_QUATERNARY_HISTOGRAM_CCA_QUATERNARY_HISTOGRAM_SET(x) (((0x0 | (x)) << HWSCH_CCA_QUATERNARY_HISTOGRAM_CCA_QUATERNARY_HISTOGRAM_LSB) & HWSCH_CCA_QUATERNARY_HISTOGRAM_CCA_QUATERNARY_HISTOGRAM_MASK)
#define HWSCH_CCA_QUATERNARY_HISTOGRAM_CCA_QUATERNARY_HISTOGRAM_RESET 0
#define HWSCH_CCA_QUATERNARY_HISTOGRAM_ADDRESS                       0x000118
#define HWSCH_CCA_QUATERNARY_HISTOGRAM_HW_MASK                       0xffffffff
#define HWSCH_CCA_QUATERNARY_HISTOGRAM_SW_MASK                       0xffffffff
#define HWSCH_CCA_QUATERNARY_HISTOGRAM_RSTMASK                       0x00000000
#define HWSCH_CCA_QUATERNARY_HISTOGRAM_RESET                         0x00000000

// 0x011c (HWSCH_CMD_RING_BASE_0)
#define HWSCH_CMD_RING_BASE_0_HWSCH_CMD_RING_BASE_DATA_MSB           31
#define HWSCH_CMD_RING_BASE_0_HWSCH_CMD_RING_BASE_DATA_LSB           0
#define HWSCH_CMD_RING_BASE_0_HWSCH_CMD_RING_BASE_DATA_MASK          0xffffffff
#define HWSCH_CMD_RING_BASE_0_HWSCH_CMD_RING_BASE_DATA_GET(x)        (((x) & HWSCH_CMD_RING_BASE_0_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_0_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_0_HWSCH_CMD_RING_BASE_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_BASE_0_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_0_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_0_HWSCH_CMD_RING_BASE_DATA_RESET         0
#define HWSCH_CMD_RING_BASE_0_ADDRESS                                0x00011c
#define HWSCH_CMD_RING_BASE_0_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_0_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_0_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_BASE_0_RESET                                  0x00000000

// 0x0120 (HWSCH_CMD_RING_BASE_1)
#define HWSCH_CMD_RING_BASE_1_HWSCH_CMD_RING_BASE_DATA_MSB           31
#define HWSCH_CMD_RING_BASE_1_HWSCH_CMD_RING_BASE_DATA_LSB           0
#define HWSCH_CMD_RING_BASE_1_HWSCH_CMD_RING_BASE_DATA_MASK          0xffffffff
#define HWSCH_CMD_RING_BASE_1_HWSCH_CMD_RING_BASE_DATA_GET(x)        (((x) & HWSCH_CMD_RING_BASE_1_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_1_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_1_HWSCH_CMD_RING_BASE_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_BASE_1_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_1_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_1_HWSCH_CMD_RING_BASE_DATA_RESET         0
#define HWSCH_CMD_RING_BASE_1_ADDRESS                                0x000120
#define HWSCH_CMD_RING_BASE_1_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_1_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_1_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_BASE_1_RESET                                  0x00000000

// 0x0124 (HWSCH_CMD_RING_BASE_2)
#define HWSCH_CMD_RING_BASE_2_HWSCH_CMD_RING_BASE_DATA_MSB           31
#define HWSCH_CMD_RING_BASE_2_HWSCH_CMD_RING_BASE_DATA_LSB           0
#define HWSCH_CMD_RING_BASE_2_HWSCH_CMD_RING_BASE_DATA_MASK          0xffffffff
#define HWSCH_CMD_RING_BASE_2_HWSCH_CMD_RING_BASE_DATA_GET(x)        (((x) & HWSCH_CMD_RING_BASE_2_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_2_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_2_HWSCH_CMD_RING_BASE_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_BASE_2_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_2_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_2_HWSCH_CMD_RING_BASE_DATA_RESET         0
#define HWSCH_CMD_RING_BASE_2_ADDRESS                                0x000124
#define HWSCH_CMD_RING_BASE_2_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_2_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_2_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_BASE_2_RESET                                  0x00000000

// 0x0128 (HWSCH_CMD_RING_BASE_3)
#define HWSCH_CMD_RING_BASE_3_HWSCH_CMD_RING_BASE_DATA_MSB           31
#define HWSCH_CMD_RING_BASE_3_HWSCH_CMD_RING_BASE_DATA_LSB           0
#define HWSCH_CMD_RING_BASE_3_HWSCH_CMD_RING_BASE_DATA_MASK          0xffffffff
#define HWSCH_CMD_RING_BASE_3_HWSCH_CMD_RING_BASE_DATA_GET(x)        (((x) & HWSCH_CMD_RING_BASE_3_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_3_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_3_HWSCH_CMD_RING_BASE_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_BASE_3_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_3_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_3_HWSCH_CMD_RING_BASE_DATA_RESET         0
#define HWSCH_CMD_RING_BASE_3_ADDRESS                                0x000128
#define HWSCH_CMD_RING_BASE_3_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_3_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_3_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_BASE_3_RESET                                  0x00000000

// 0x012c (HWSCH_CMD_RING_BASE_4)
#define HWSCH_CMD_RING_BASE_4_HWSCH_CMD_RING_BASE_DATA_MSB           31
#define HWSCH_CMD_RING_BASE_4_HWSCH_CMD_RING_BASE_DATA_LSB           0
#define HWSCH_CMD_RING_BASE_4_HWSCH_CMD_RING_BASE_DATA_MASK          0xffffffff
#define HWSCH_CMD_RING_BASE_4_HWSCH_CMD_RING_BASE_DATA_GET(x)        (((x) & HWSCH_CMD_RING_BASE_4_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_4_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_4_HWSCH_CMD_RING_BASE_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_BASE_4_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_4_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_4_HWSCH_CMD_RING_BASE_DATA_RESET         0
#define HWSCH_CMD_RING_BASE_4_ADDRESS                                0x00012c
#define HWSCH_CMD_RING_BASE_4_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_4_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_4_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_BASE_4_RESET                                  0x00000000

// 0x0130 (HWSCH_CMD_RING_BASE_5)
#define HWSCH_CMD_RING_BASE_5_HWSCH_CMD_RING_BASE_DATA_MSB           31
#define HWSCH_CMD_RING_BASE_5_HWSCH_CMD_RING_BASE_DATA_LSB           0
#define HWSCH_CMD_RING_BASE_5_HWSCH_CMD_RING_BASE_DATA_MASK          0xffffffff
#define HWSCH_CMD_RING_BASE_5_HWSCH_CMD_RING_BASE_DATA_GET(x)        (((x) & HWSCH_CMD_RING_BASE_5_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_5_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_5_HWSCH_CMD_RING_BASE_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_BASE_5_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_5_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_5_HWSCH_CMD_RING_BASE_DATA_RESET         0
#define HWSCH_CMD_RING_BASE_5_ADDRESS                                0x000130
#define HWSCH_CMD_RING_BASE_5_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_5_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_5_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_BASE_5_RESET                                  0x00000000

// 0x0134 (HWSCH_CMD_RING_BASE_6)
#define HWSCH_CMD_RING_BASE_6_HWSCH_CMD_RING_BASE_DATA_MSB           31
#define HWSCH_CMD_RING_BASE_6_HWSCH_CMD_RING_BASE_DATA_LSB           0
#define HWSCH_CMD_RING_BASE_6_HWSCH_CMD_RING_BASE_DATA_MASK          0xffffffff
#define HWSCH_CMD_RING_BASE_6_HWSCH_CMD_RING_BASE_DATA_GET(x)        (((x) & HWSCH_CMD_RING_BASE_6_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_6_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_6_HWSCH_CMD_RING_BASE_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_BASE_6_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_6_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_6_HWSCH_CMD_RING_BASE_DATA_RESET         0
#define HWSCH_CMD_RING_BASE_6_ADDRESS                                0x000134
#define HWSCH_CMD_RING_BASE_6_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_6_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_6_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_BASE_6_RESET                                  0x00000000

// 0x0138 (HWSCH_CMD_RING_BASE_7)
#define HWSCH_CMD_RING_BASE_7_HWSCH_CMD_RING_BASE_DATA_MSB           31
#define HWSCH_CMD_RING_BASE_7_HWSCH_CMD_RING_BASE_DATA_LSB           0
#define HWSCH_CMD_RING_BASE_7_HWSCH_CMD_RING_BASE_DATA_MASK          0xffffffff
#define HWSCH_CMD_RING_BASE_7_HWSCH_CMD_RING_BASE_DATA_GET(x)        (((x) & HWSCH_CMD_RING_BASE_7_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_7_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_7_HWSCH_CMD_RING_BASE_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_BASE_7_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_7_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_7_HWSCH_CMD_RING_BASE_DATA_RESET         0
#define HWSCH_CMD_RING_BASE_7_ADDRESS                                0x000138
#define HWSCH_CMD_RING_BASE_7_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_7_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_7_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_BASE_7_RESET                                  0x00000000

// 0x013c (HWSCH_CMD_RING_BASE_8)
#define HWSCH_CMD_RING_BASE_8_HWSCH_CMD_RING_BASE_DATA_MSB           31
#define HWSCH_CMD_RING_BASE_8_HWSCH_CMD_RING_BASE_DATA_LSB           0
#define HWSCH_CMD_RING_BASE_8_HWSCH_CMD_RING_BASE_DATA_MASK          0xffffffff
#define HWSCH_CMD_RING_BASE_8_HWSCH_CMD_RING_BASE_DATA_GET(x)        (((x) & HWSCH_CMD_RING_BASE_8_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_8_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_8_HWSCH_CMD_RING_BASE_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_BASE_8_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_8_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_8_HWSCH_CMD_RING_BASE_DATA_RESET         0
#define HWSCH_CMD_RING_BASE_8_ADDRESS                                0x00013c
#define HWSCH_CMD_RING_BASE_8_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_8_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_8_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_BASE_8_RESET                                  0x00000000

// 0x0140 (HWSCH_CMD_RING_BASE_9)
#define HWSCH_CMD_RING_BASE_9_HWSCH_CMD_RING_BASE_DATA_MSB           31
#define HWSCH_CMD_RING_BASE_9_HWSCH_CMD_RING_BASE_DATA_LSB           0
#define HWSCH_CMD_RING_BASE_9_HWSCH_CMD_RING_BASE_DATA_MASK          0xffffffff
#define HWSCH_CMD_RING_BASE_9_HWSCH_CMD_RING_BASE_DATA_GET(x)        (((x) & HWSCH_CMD_RING_BASE_9_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_9_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_9_HWSCH_CMD_RING_BASE_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_BASE_9_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_9_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_9_HWSCH_CMD_RING_BASE_DATA_RESET         0
#define HWSCH_CMD_RING_BASE_9_ADDRESS                                0x000140
#define HWSCH_CMD_RING_BASE_9_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_9_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_BASE_9_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_BASE_9_RESET                                  0x00000000

// 0x0144 (HWSCH_CMD_RING_BASE_10)
#define HWSCH_CMD_RING_BASE_10_HWSCH_CMD_RING_BASE_DATA_MSB          31
#define HWSCH_CMD_RING_BASE_10_HWSCH_CMD_RING_BASE_DATA_LSB          0
#define HWSCH_CMD_RING_BASE_10_HWSCH_CMD_RING_BASE_DATA_MASK         0xffffffff
#define HWSCH_CMD_RING_BASE_10_HWSCH_CMD_RING_BASE_DATA_GET(x)       (((x) & HWSCH_CMD_RING_BASE_10_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_10_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_10_HWSCH_CMD_RING_BASE_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_BASE_10_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_10_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_10_HWSCH_CMD_RING_BASE_DATA_RESET        0
#define HWSCH_CMD_RING_BASE_10_ADDRESS                               0x000144
#define HWSCH_CMD_RING_BASE_10_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_10_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_10_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_BASE_10_RESET                                 0x00000000

// 0x0148 (HWSCH_CMD_RING_BASE_11)
#define HWSCH_CMD_RING_BASE_11_HWSCH_CMD_RING_BASE_DATA_MSB          31
#define HWSCH_CMD_RING_BASE_11_HWSCH_CMD_RING_BASE_DATA_LSB          0
#define HWSCH_CMD_RING_BASE_11_HWSCH_CMD_RING_BASE_DATA_MASK         0xffffffff
#define HWSCH_CMD_RING_BASE_11_HWSCH_CMD_RING_BASE_DATA_GET(x)       (((x) & HWSCH_CMD_RING_BASE_11_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_11_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_11_HWSCH_CMD_RING_BASE_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_BASE_11_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_11_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_11_HWSCH_CMD_RING_BASE_DATA_RESET        0
#define HWSCH_CMD_RING_BASE_11_ADDRESS                               0x000148
#define HWSCH_CMD_RING_BASE_11_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_11_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_11_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_BASE_11_RESET                                 0x00000000

// 0x014c (HWSCH_CMD_RING_BASE_12)
#define HWSCH_CMD_RING_BASE_12_HWSCH_CMD_RING_BASE_DATA_MSB          31
#define HWSCH_CMD_RING_BASE_12_HWSCH_CMD_RING_BASE_DATA_LSB          0
#define HWSCH_CMD_RING_BASE_12_HWSCH_CMD_RING_BASE_DATA_MASK         0xffffffff
#define HWSCH_CMD_RING_BASE_12_HWSCH_CMD_RING_BASE_DATA_GET(x)       (((x) & HWSCH_CMD_RING_BASE_12_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_12_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_12_HWSCH_CMD_RING_BASE_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_BASE_12_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_12_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_12_HWSCH_CMD_RING_BASE_DATA_RESET        0
#define HWSCH_CMD_RING_BASE_12_ADDRESS                               0x00014c
#define HWSCH_CMD_RING_BASE_12_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_12_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_12_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_BASE_12_RESET                                 0x00000000

// 0x0150 (HWSCH_CMD_RING_BASE_13)
#define HWSCH_CMD_RING_BASE_13_HWSCH_CMD_RING_BASE_DATA_MSB          31
#define HWSCH_CMD_RING_BASE_13_HWSCH_CMD_RING_BASE_DATA_LSB          0
#define HWSCH_CMD_RING_BASE_13_HWSCH_CMD_RING_BASE_DATA_MASK         0xffffffff
#define HWSCH_CMD_RING_BASE_13_HWSCH_CMD_RING_BASE_DATA_GET(x)       (((x) & HWSCH_CMD_RING_BASE_13_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_13_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_13_HWSCH_CMD_RING_BASE_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_BASE_13_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_13_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_13_HWSCH_CMD_RING_BASE_DATA_RESET        0
#define HWSCH_CMD_RING_BASE_13_ADDRESS                               0x000150
#define HWSCH_CMD_RING_BASE_13_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_13_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_13_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_BASE_13_RESET                                 0x00000000

// 0x0154 (HWSCH_CMD_RING_BASE_14)
#define HWSCH_CMD_RING_BASE_14_HWSCH_CMD_RING_BASE_DATA_MSB          31
#define HWSCH_CMD_RING_BASE_14_HWSCH_CMD_RING_BASE_DATA_LSB          0
#define HWSCH_CMD_RING_BASE_14_HWSCH_CMD_RING_BASE_DATA_MASK         0xffffffff
#define HWSCH_CMD_RING_BASE_14_HWSCH_CMD_RING_BASE_DATA_GET(x)       (((x) & HWSCH_CMD_RING_BASE_14_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_14_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_14_HWSCH_CMD_RING_BASE_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_BASE_14_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_14_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_14_HWSCH_CMD_RING_BASE_DATA_RESET        0
#define HWSCH_CMD_RING_BASE_14_ADDRESS                               0x000154
#define HWSCH_CMD_RING_BASE_14_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_14_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_14_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_BASE_14_RESET                                 0x00000000

// 0x0158 (HWSCH_CMD_RING_BASE_15)
#define HWSCH_CMD_RING_BASE_15_HWSCH_CMD_RING_BASE_DATA_MSB          31
#define HWSCH_CMD_RING_BASE_15_HWSCH_CMD_RING_BASE_DATA_LSB          0
#define HWSCH_CMD_RING_BASE_15_HWSCH_CMD_RING_BASE_DATA_MASK         0xffffffff
#define HWSCH_CMD_RING_BASE_15_HWSCH_CMD_RING_BASE_DATA_GET(x)       (((x) & HWSCH_CMD_RING_BASE_15_HWSCH_CMD_RING_BASE_DATA_MASK) >> HWSCH_CMD_RING_BASE_15_HWSCH_CMD_RING_BASE_DATA_LSB)
#define HWSCH_CMD_RING_BASE_15_HWSCH_CMD_RING_BASE_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_BASE_15_HWSCH_CMD_RING_BASE_DATA_LSB) & HWSCH_CMD_RING_BASE_15_HWSCH_CMD_RING_BASE_DATA_MASK)
#define HWSCH_CMD_RING_BASE_15_HWSCH_CMD_RING_BASE_DATA_RESET        0
#define HWSCH_CMD_RING_BASE_15_ADDRESS                               0x000158
#define HWSCH_CMD_RING_BASE_15_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_15_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_BASE_15_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_BASE_15_RESET                                 0x00000000

// 0x015c (HWSCH_CMD_RING_NUM_ENTRY_0)
#define HWSCH_CMD_RING_NUM_ENTRY_0_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_NUM_ENTRY_0_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_NUM_ENTRY_0_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_0_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_NUM_ENTRY_0_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_0_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_0_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_0_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_0_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_0_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_NUM_ENTRY_0_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_0_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_0_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_0_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_0_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_0_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_0_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_0_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_0_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_0_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_0_ADDRESS                           0x00015c
#define HWSCH_CMD_RING_NUM_ENTRY_0_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_0_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_0_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_0_RESET                             0x00000100

// 0x0160 (HWSCH_CMD_RING_NUM_ENTRY_1)
#define HWSCH_CMD_RING_NUM_ENTRY_1_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_NUM_ENTRY_1_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_NUM_ENTRY_1_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_1_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_NUM_ENTRY_1_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_1_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_1_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_1_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_1_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_1_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_NUM_ENTRY_1_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_1_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_1_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_1_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_1_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_1_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_1_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_1_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_1_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_1_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_1_ADDRESS                           0x000160
#define HWSCH_CMD_RING_NUM_ENTRY_1_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_1_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_1_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_1_RESET                             0x00000100

// 0x0164 (HWSCH_CMD_RING_NUM_ENTRY_2)
#define HWSCH_CMD_RING_NUM_ENTRY_2_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_NUM_ENTRY_2_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_NUM_ENTRY_2_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_2_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_NUM_ENTRY_2_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_2_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_2_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_2_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_2_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_2_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_NUM_ENTRY_2_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_2_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_2_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_2_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_2_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_2_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_2_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_2_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_2_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_2_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_2_ADDRESS                           0x000164
#define HWSCH_CMD_RING_NUM_ENTRY_2_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_2_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_2_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_2_RESET                             0x00000100

// 0x0168 (HWSCH_CMD_RING_NUM_ENTRY_3)
#define HWSCH_CMD_RING_NUM_ENTRY_3_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_NUM_ENTRY_3_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_NUM_ENTRY_3_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_3_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_NUM_ENTRY_3_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_3_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_3_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_3_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_3_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_3_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_NUM_ENTRY_3_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_3_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_3_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_3_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_3_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_3_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_3_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_3_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_3_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_3_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_3_ADDRESS                           0x000168
#define HWSCH_CMD_RING_NUM_ENTRY_3_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_3_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_3_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_3_RESET                             0x00000100

// 0x016c (HWSCH_CMD_RING_NUM_ENTRY_4)
#define HWSCH_CMD_RING_NUM_ENTRY_4_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_NUM_ENTRY_4_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_NUM_ENTRY_4_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_4_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_NUM_ENTRY_4_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_4_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_4_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_4_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_4_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_4_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_NUM_ENTRY_4_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_4_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_4_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_4_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_4_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_4_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_4_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_4_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_4_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_4_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_4_ADDRESS                           0x00016c
#define HWSCH_CMD_RING_NUM_ENTRY_4_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_4_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_4_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_4_RESET                             0x00000100

// 0x0170 (HWSCH_CMD_RING_NUM_ENTRY_5)
#define HWSCH_CMD_RING_NUM_ENTRY_5_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_NUM_ENTRY_5_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_NUM_ENTRY_5_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_5_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_NUM_ENTRY_5_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_5_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_5_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_5_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_5_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_5_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_NUM_ENTRY_5_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_5_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_5_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_5_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_5_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_5_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_5_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_5_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_5_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_5_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_5_ADDRESS                           0x000170
#define HWSCH_CMD_RING_NUM_ENTRY_5_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_5_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_5_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_5_RESET                             0x00000100

// 0x0174 (HWSCH_CMD_RING_NUM_ENTRY_6)
#define HWSCH_CMD_RING_NUM_ENTRY_6_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_NUM_ENTRY_6_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_NUM_ENTRY_6_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_6_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_NUM_ENTRY_6_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_6_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_6_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_6_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_6_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_6_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_NUM_ENTRY_6_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_6_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_6_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_6_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_6_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_6_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_6_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_6_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_6_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_6_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_6_ADDRESS                           0x000174
#define HWSCH_CMD_RING_NUM_ENTRY_6_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_6_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_6_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_6_RESET                             0x00000100

// 0x0178 (HWSCH_CMD_RING_NUM_ENTRY_7)
#define HWSCH_CMD_RING_NUM_ENTRY_7_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_NUM_ENTRY_7_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_NUM_ENTRY_7_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_7_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_NUM_ENTRY_7_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_7_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_7_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_7_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_7_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_7_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_NUM_ENTRY_7_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_7_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_7_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_7_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_7_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_7_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_7_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_7_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_7_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_7_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_7_ADDRESS                           0x000178
#define HWSCH_CMD_RING_NUM_ENTRY_7_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_7_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_7_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_7_RESET                             0x00000100

// 0x017c (HWSCH_CMD_RING_NUM_ENTRY_8)
#define HWSCH_CMD_RING_NUM_ENTRY_8_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_NUM_ENTRY_8_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_NUM_ENTRY_8_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_8_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_NUM_ENTRY_8_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_8_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_8_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_8_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_8_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_8_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_NUM_ENTRY_8_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_8_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_8_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_8_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_8_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_8_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_8_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_8_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_8_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_8_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_8_ADDRESS                           0x00017c
#define HWSCH_CMD_RING_NUM_ENTRY_8_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_8_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_8_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_8_RESET                             0x00000100

// 0x0180 (HWSCH_CMD_RING_NUM_ENTRY_9)
#define HWSCH_CMD_RING_NUM_ENTRY_9_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_NUM_ENTRY_9_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_NUM_ENTRY_9_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_9_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_NUM_ENTRY_9_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_9_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_9_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_9_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_9_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_9_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_NUM_ENTRY_9_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_9_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_9_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_9_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_9_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_9_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_9_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_9_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_9_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_9_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_9_ADDRESS                           0x000180
#define HWSCH_CMD_RING_NUM_ENTRY_9_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_9_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_9_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_9_RESET                             0x00000100

// 0x0184 (HWSCH_CMD_RING_NUM_ENTRY_10)
#define HWSCH_CMD_RING_NUM_ENTRY_10_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_NUM_ENTRY_10_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_NUM_ENTRY_10_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_10_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_NUM_ENTRY_10_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_10_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_10_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_10_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_10_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_10_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_NUM_ENTRY_10_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_10_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_10_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_10_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_10_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_10_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_10_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_10_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_10_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_10_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_10_ADDRESS                          0x000184
#define HWSCH_CMD_RING_NUM_ENTRY_10_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_10_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_10_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_10_RESET                            0x00000100

// 0x0188 (HWSCH_CMD_RING_NUM_ENTRY_11)
#define HWSCH_CMD_RING_NUM_ENTRY_11_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_NUM_ENTRY_11_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_NUM_ENTRY_11_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_11_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_NUM_ENTRY_11_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_11_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_11_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_11_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_11_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_11_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_NUM_ENTRY_11_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_11_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_11_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_11_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_11_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_11_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_11_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_11_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_11_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_11_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_11_ADDRESS                          0x000188
#define HWSCH_CMD_RING_NUM_ENTRY_11_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_11_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_11_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_11_RESET                            0x00000100

// 0x018c (HWSCH_CMD_RING_NUM_ENTRY_12)
#define HWSCH_CMD_RING_NUM_ENTRY_12_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_NUM_ENTRY_12_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_NUM_ENTRY_12_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_12_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_NUM_ENTRY_12_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_12_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_12_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_12_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_12_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_12_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_NUM_ENTRY_12_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_12_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_12_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_12_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_12_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_12_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_12_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_12_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_12_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_12_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_12_ADDRESS                          0x00018c
#define HWSCH_CMD_RING_NUM_ENTRY_12_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_12_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_12_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_12_RESET                            0x00000100

// 0x0190 (HWSCH_CMD_RING_NUM_ENTRY_13)
#define HWSCH_CMD_RING_NUM_ENTRY_13_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_NUM_ENTRY_13_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_NUM_ENTRY_13_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_13_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_NUM_ENTRY_13_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_13_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_13_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_13_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_13_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_13_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_NUM_ENTRY_13_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_13_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_13_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_13_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_13_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_13_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_13_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_13_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_13_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_13_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_13_ADDRESS                          0x000190
#define HWSCH_CMD_RING_NUM_ENTRY_13_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_13_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_13_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_13_RESET                            0x00000100

// 0x0194 (HWSCH_CMD_RING_NUM_ENTRY_14)
#define HWSCH_CMD_RING_NUM_ENTRY_14_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_NUM_ENTRY_14_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_NUM_ENTRY_14_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_14_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_NUM_ENTRY_14_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_14_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_14_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_14_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_14_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_14_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_NUM_ENTRY_14_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_14_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_14_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_14_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_14_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_14_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_14_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_14_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_14_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_14_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_14_ADDRESS                          0x000194
#define HWSCH_CMD_RING_NUM_ENTRY_14_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_14_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_14_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_14_RESET                            0x00000100

// 0x0198 (HWSCH_CMD_RING_NUM_ENTRY_15)
#define HWSCH_CMD_RING_NUM_ENTRY_15_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_NUM_ENTRY_15_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_NUM_ENTRY_15_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_NUM_ENTRY_15_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_NUM_ENTRY_15_RESERVED_0_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_15_RESERVED_0_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_15_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_15_RESERVED_0_LSB) & HWSCH_CMD_RING_NUM_ENTRY_15_RESERVED_0_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_15_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_NUM_ENTRY_15_HWSCH_CMD_RING_NUM_ENTRY_DATA_MSB 15
#define HWSCH_CMD_RING_NUM_ENTRY_15_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB 0
#define HWSCH_CMD_RING_NUM_ENTRY_15_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_15_HWSCH_CMD_RING_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_CMD_RING_NUM_ENTRY_15_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK) >> HWSCH_CMD_RING_NUM_ENTRY_15_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB)
#define HWSCH_CMD_RING_NUM_ENTRY_15_HWSCH_CMD_RING_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_NUM_ENTRY_15_HWSCH_CMD_RING_NUM_ENTRY_DATA_LSB) & HWSCH_CMD_RING_NUM_ENTRY_15_HWSCH_CMD_RING_NUM_ENTRY_DATA_MASK)
#define HWSCH_CMD_RING_NUM_ENTRY_15_HWSCH_CMD_RING_NUM_ENTRY_DATA_RESET 256
#define HWSCH_CMD_RING_NUM_ENTRY_15_ADDRESS                          0x000198
#define HWSCH_CMD_RING_NUM_ENTRY_15_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_15_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_NUM_ENTRY_15_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_NUM_ENTRY_15_RESET                            0x00000100

// 0x019c (HWSCH_CMD_RING_HEAD_0)
#define HWSCH_CMD_RING_HEAD_0_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_HEAD_0_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_HEAD_0_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_HEAD_0_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_HEAD_0_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_0_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_0_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_0_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_0_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_0_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_HEAD_0_HWSCH_CMD_RING_HEAD_DATA_MSB           15
#define HWSCH_CMD_RING_HEAD_0_HWSCH_CMD_RING_HEAD_DATA_LSB           0
#define HWSCH_CMD_RING_HEAD_0_HWSCH_CMD_RING_HEAD_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_HEAD_0_HWSCH_CMD_RING_HEAD_DATA_GET(x)        (((x) & HWSCH_CMD_RING_HEAD_0_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_0_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_0_HWSCH_CMD_RING_HEAD_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_0_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_0_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_0_HWSCH_CMD_RING_HEAD_DATA_RESET         0
#define HWSCH_CMD_RING_HEAD_0_ADDRESS                                0x00019c
#define HWSCH_CMD_RING_HEAD_0_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_0_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_0_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_HEAD_0_RESET                                  0x00000000

// 0x01a0 (HWSCH_CMD_RING_HEAD_1)
#define HWSCH_CMD_RING_HEAD_1_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_HEAD_1_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_HEAD_1_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_HEAD_1_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_HEAD_1_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_1_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_1_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_1_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_1_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_1_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_HEAD_1_HWSCH_CMD_RING_HEAD_DATA_MSB           15
#define HWSCH_CMD_RING_HEAD_1_HWSCH_CMD_RING_HEAD_DATA_LSB           0
#define HWSCH_CMD_RING_HEAD_1_HWSCH_CMD_RING_HEAD_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_HEAD_1_HWSCH_CMD_RING_HEAD_DATA_GET(x)        (((x) & HWSCH_CMD_RING_HEAD_1_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_1_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_1_HWSCH_CMD_RING_HEAD_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_1_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_1_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_1_HWSCH_CMD_RING_HEAD_DATA_RESET         0
#define HWSCH_CMD_RING_HEAD_1_ADDRESS                                0x0001a0
#define HWSCH_CMD_RING_HEAD_1_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_1_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_1_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_HEAD_1_RESET                                  0x00000000

// 0x01a4 (HWSCH_CMD_RING_HEAD_2)
#define HWSCH_CMD_RING_HEAD_2_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_HEAD_2_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_HEAD_2_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_HEAD_2_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_HEAD_2_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_2_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_2_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_2_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_2_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_2_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_HEAD_2_HWSCH_CMD_RING_HEAD_DATA_MSB           15
#define HWSCH_CMD_RING_HEAD_2_HWSCH_CMD_RING_HEAD_DATA_LSB           0
#define HWSCH_CMD_RING_HEAD_2_HWSCH_CMD_RING_HEAD_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_HEAD_2_HWSCH_CMD_RING_HEAD_DATA_GET(x)        (((x) & HWSCH_CMD_RING_HEAD_2_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_2_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_2_HWSCH_CMD_RING_HEAD_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_2_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_2_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_2_HWSCH_CMD_RING_HEAD_DATA_RESET         0
#define HWSCH_CMD_RING_HEAD_2_ADDRESS                                0x0001a4
#define HWSCH_CMD_RING_HEAD_2_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_2_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_2_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_HEAD_2_RESET                                  0x00000000

// 0x01a8 (HWSCH_CMD_RING_HEAD_3)
#define HWSCH_CMD_RING_HEAD_3_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_HEAD_3_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_HEAD_3_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_HEAD_3_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_HEAD_3_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_3_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_3_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_3_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_3_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_3_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_HEAD_3_HWSCH_CMD_RING_HEAD_DATA_MSB           15
#define HWSCH_CMD_RING_HEAD_3_HWSCH_CMD_RING_HEAD_DATA_LSB           0
#define HWSCH_CMD_RING_HEAD_3_HWSCH_CMD_RING_HEAD_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_HEAD_3_HWSCH_CMD_RING_HEAD_DATA_GET(x)        (((x) & HWSCH_CMD_RING_HEAD_3_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_3_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_3_HWSCH_CMD_RING_HEAD_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_3_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_3_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_3_HWSCH_CMD_RING_HEAD_DATA_RESET         0
#define HWSCH_CMD_RING_HEAD_3_ADDRESS                                0x0001a8
#define HWSCH_CMD_RING_HEAD_3_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_3_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_3_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_HEAD_3_RESET                                  0x00000000

// 0x01ac (HWSCH_CMD_RING_HEAD_4)
#define HWSCH_CMD_RING_HEAD_4_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_HEAD_4_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_HEAD_4_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_HEAD_4_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_HEAD_4_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_4_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_4_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_4_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_4_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_4_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_HEAD_4_HWSCH_CMD_RING_HEAD_DATA_MSB           15
#define HWSCH_CMD_RING_HEAD_4_HWSCH_CMD_RING_HEAD_DATA_LSB           0
#define HWSCH_CMD_RING_HEAD_4_HWSCH_CMD_RING_HEAD_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_HEAD_4_HWSCH_CMD_RING_HEAD_DATA_GET(x)        (((x) & HWSCH_CMD_RING_HEAD_4_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_4_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_4_HWSCH_CMD_RING_HEAD_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_4_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_4_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_4_HWSCH_CMD_RING_HEAD_DATA_RESET         0
#define HWSCH_CMD_RING_HEAD_4_ADDRESS                                0x0001ac
#define HWSCH_CMD_RING_HEAD_4_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_4_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_4_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_HEAD_4_RESET                                  0x00000000

// 0x01b0 (HWSCH_CMD_RING_HEAD_5)
#define HWSCH_CMD_RING_HEAD_5_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_HEAD_5_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_HEAD_5_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_HEAD_5_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_HEAD_5_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_5_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_5_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_5_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_5_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_5_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_HEAD_5_HWSCH_CMD_RING_HEAD_DATA_MSB           15
#define HWSCH_CMD_RING_HEAD_5_HWSCH_CMD_RING_HEAD_DATA_LSB           0
#define HWSCH_CMD_RING_HEAD_5_HWSCH_CMD_RING_HEAD_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_HEAD_5_HWSCH_CMD_RING_HEAD_DATA_GET(x)        (((x) & HWSCH_CMD_RING_HEAD_5_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_5_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_5_HWSCH_CMD_RING_HEAD_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_5_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_5_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_5_HWSCH_CMD_RING_HEAD_DATA_RESET         0
#define HWSCH_CMD_RING_HEAD_5_ADDRESS                                0x0001b0
#define HWSCH_CMD_RING_HEAD_5_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_5_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_5_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_HEAD_5_RESET                                  0x00000000

// 0x01b4 (HWSCH_CMD_RING_HEAD_6)
#define HWSCH_CMD_RING_HEAD_6_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_HEAD_6_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_HEAD_6_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_HEAD_6_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_HEAD_6_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_6_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_6_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_6_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_6_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_6_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_HEAD_6_HWSCH_CMD_RING_HEAD_DATA_MSB           15
#define HWSCH_CMD_RING_HEAD_6_HWSCH_CMD_RING_HEAD_DATA_LSB           0
#define HWSCH_CMD_RING_HEAD_6_HWSCH_CMD_RING_HEAD_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_HEAD_6_HWSCH_CMD_RING_HEAD_DATA_GET(x)        (((x) & HWSCH_CMD_RING_HEAD_6_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_6_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_6_HWSCH_CMD_RING_HEAD_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_6_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_6_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_6_HWSCH_CMD_RING_HEAD_DATA_RESET         0
#define HWSCH_CMD_RING_HEAD_6_ADDRESS                                0x0001b4
#define HWSCH_CMD_RING_HEAD_6_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_6_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_6_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_HEAD_6_RESET                                  0x00000000

// 0x01b8 (HWSCH_CMD_RING_HEAD_7)
#define HWSCH_CMD_RING_HEAD_7_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_HEAD_7_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_HEAD_7_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_HEAD_7_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_HEAD_7_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_7_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_7_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_7_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_7_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_7_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_HEAD_7_HWSCH_CMD_RING_HEAD_DATA_MSB           15
#define HWSCH_CMD_RING_HEAD_7_HWSCH_CMD_RING_HEAD_DATA_LSB           0
#define HWSCH_CMD_RING_HEAD_7_HWSCH_CMD_RING_HEAD_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_HEAD_7_HWSCH_CMD_RING_HEAD_DATA_GET(x)        (((x) & HWSCH_CMD_RING_HEAD_7_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_7_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_7_HWSCH_CMD_RING_HEAD_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_7_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_7_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_7_HWSCH_CMD_RING_HEAD_DATA_RESET         0
#define HWSCH_CMD_RING_HEAD_7_ADDRESS                                0x0001b8
#define HWSCH_CMD_RING_HEAD_7_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_7_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_7_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_HEAD_7_RESET                                  0x00000000

// 0x01bc (HWSCH_CMD_RING_HEAD_8)
#define HWSCH_CMD_RING_HEAD_8_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_HEAD_8_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_HEAD_8_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_HEAD_8_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_HEAD_8_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_8_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_8_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_8_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_8_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_8_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_HEAD_8_HWSCH_CMD_RING_HEAD_DATA_MSB           15
#define HWSCH_CMD_RING_HEAD_8_HWSCH_CMD_RING_HEAD_DATA_LSB           0
#define HWSCH_CMD_RING_HEAD_8_HWSCH_CMD_RING_HEAD_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_HEAD_8_HWSCH_CMD_RING_HEAD_DATA_GET(x)        (((x) & HWSCH_CMD_RING_HEAD_8_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_8_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_8_HWSCH_CMD_RING_HEAD_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_8_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_8_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_8_HWSCH_CMD_RING_HEAD_DATA_RESET         0
#define HWSCH_CMD_RING_HEAD_8_ADDRESS                                0x0001bc
#define HWSCH_CMD_RING_HEAD_8_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_8_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_8_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_HEAD_8_RESET                                  0x00000000

// 0x01c0 (HWSCH_CMD_RING_HEAD_9)
#define HWSCH_CMD_RING_HEAD_9_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_HEAD_9_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_HEAD_9_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_HEAD_9_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_HEAD_9_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_9_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_9_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_9_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_9_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_9_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_HEAD_9_HWSCH_CMD_RING_HEAD_DATA_MSB           15
#define HWSCH_CMD_RING_HEAD_9_HWSCH_CMD_RING_HEAD_DATA_LSB           0
#define HWSCH_CMD_RING_HEAD_9_HWSCH_CMD_RING_HEAD_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_HEAD_9_HWSCH_CMD_RING_HEAD_DATA_GET(x)        (((x) & HWSCH_CMD_RING_HEAD_9_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_9_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_9_HWSCH_CMD_RING_HEAD_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_9_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_9_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_9_HWSCH_CMD_RING_HEAD_DATA_RESET         0
#define HWSCH_CMD_RING_HEAD_9_ADDRESS                                0x0001c0
#define HWSCH_CMD_RING_HEAD_9_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_9_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_HEAD_9_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_HEAD_9_RESET                                  0x00000000

// 0x01c4 (HWSCH_CMD_RING_HEAD_10)
#define HWSCH_CMD_RING_HEAD_10_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_HEAD_10_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_HEAD_10_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_HEAD_10_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_HEAD_10_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_10_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_10_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_10_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_10_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_10_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_HEAD_10_HWSCH_CMD_RING_HEAD_DATA_MSB          15
#define HWSCH_CMD_RING_HEAD_10_HWSCH_CMD_RING_HEAD_DATA_LSB          0
#define HWSCH_CMD_RING_HEAD_10_HWSCH_CMD_RING_HEAD_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_HEAD_10_HWSCH_CMD_RING_HEAD_DATA_GET(x)       (((x) & HWSCH_CMD_RING_HEAD_10_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_10_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_10_HWSCH_CMD_RING_HEAD_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_10_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_10_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_10_HWSCH_CMD_RING_HEAD_DATA_RESET        0
#define HWSCH_CMD_RING_HEAD_10_ADDRESS                               0x0001c4
#define HWSCH_CMD_RING_HEAD_10_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_10_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_10_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_HEAD_10_RESET                                 0x00000000

// 0x01c8 (HWSCH_CMD_RING_HEAD_11)
#define HWSCH_CMD_RING_HEAD_11_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_HEAD_11_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_HEAD_11_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_HEAD_11_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_HEAD_11_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_11_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_11_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_11_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_11_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_11_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_HEAD_11_HWSCH_CMD_RING_HEAD_DATA_MSB          15
#define HWSCH_CMD_RING_HEAD_11_HWSCH_CMD_RING_HEAD_DATA_LSB          0
#define HWSCH_CMD_RING_HEAD_11_HWSCH_CMD_RING_HEAD_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_HEAD_11_HWSCH_CMD_RING_HEAD_DATA_GET(x)       (((x) & HWSCH_CMD_RING_HEAD_11_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_11_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_11_HWSCH_CMD_RING_HEAD_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_11_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_11_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_11_HWSCH_CMD_RING_HEAD_DATA_RESET        0
#define HWSCH_CMD_RING_HEAD_11_ADDRESS                               0x0001c8
#define HWSCH_CMD_RING_HEAD_11_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_11_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_11_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_HEAD_11_RESET                                 0x00000000

// 0x01cc (HWSCH_CMD_RING_HEAD_12)
#define HWSCH_CMD_RING_HEAD_12_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_HEAD_12_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_HEAD_12_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_HEAD_12_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_HEAD_12_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_12_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_12_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_12_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_12_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_12_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_HEAD_12_HWSCH_CMD_RING_HEAD_DATA_MSB          15
#define HWSCH_CMD_RING_HEAD_12_HWSCH_CMD_RING_HEAD_DATA_LSB          0
#define HWSCH_CMD_RING_HEAD_12_HWSCH_CMD_RING_HEAD_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_HEAD_12_HWSCH_CMD_RING_HEAD_DATA_GET(x)       (((x) & HWSCH_CMD_RING_HEAD_12_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_12_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_12_HWSCH_CMD_RING_HEAD_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_12_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_12_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_12_HWSCH_CMD_RING_HEAD_DATA_RESET        0
#define HWSCH_CMD_RING_HEAD_12_ADDRESS                               0x0001cc
#define HWSCH_CMD_RING_HEAD_12_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_12_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_12_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_HEAD_12_RESET                                 0x00000000

// 0x01d0 (HWSCH_CMD_RING_HEAD_13)
#define HWSCH_CMD_RING_HEAD_13_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_HEAD_13_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_HEAD_13_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_HEAD_13_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_HEAD_13_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_13_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_13_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_13_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_13_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_13_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_HEAD_13_HWSCH_CMD_RING_HEAD_DATA_MSB          15
#define HWSCH_CMD_RING_HEAD_13_HWSCH_CMD_RING_HEAD_DATA_LSB          0
#define HWSCH_CMD_RING_HEAD_13_HWSCH_CMD_RING_HEAD_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_HEAD_13_HWSCH_CMD_RING_HEAD_DATA_GET(x)       (((x) & HWSCH_CMD_RING_HEAD_13_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_13_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_13_HWSCH_CMD_RING_HEAD_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_13_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_13_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_13_HWSCH_CMD_RING_HEAD_DATA_RESET        0
#define HWSCH_CMD_RING_HEAD_13_ADDRESS                               0x0001d0
#define HWSCH_CMD_RING_HEAD_13_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_13_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_13_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_HEAD_13_RESET                                 0x00000000

// 0x01d4 (HWSCH_CMD_RING_HEAD_14)
#define HWSCH_CMD_RING_HEAD_14_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_HEAD_14_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_HEAD_14_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_HEAD_14_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_HEAD_14_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_14_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_14_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_14_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_14_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_14_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_HEAD_14_HWSCH_CMD_RING_HEAD_DATA_MSB          15
#define HWSCH_CMD_RING_HEAD_14_HWSCH_CMD_RING_HEAD_DATA_LSB          0
#define HWSCH_CMD_RING_HEAD_14_HWSCH_CMD_RING_HEAD_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_HEAD_14_HWSCH_CMD_RING_HEAD_DATA_GET(x)       (((x) & HWSCH_CMD_RING_HEAD_14_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_14_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_14_HWSCH_CMD_RING_HEAD_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_14_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_14_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_14_HWSCH_CMD_RING_HEAD_DATA_RESET        0
#define HWSCH_CMD_RING_HEAD_14_ADDRESS                               0x0001d4
#define HWSCH_CMD_RING_HEAD_14_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_14_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_14_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_HEAD_14_RESET                                 0x00000000

// 0x01d8 (HWSCH_CMD_RING_HEAD_15)
#define HWSCH_CMD_RING_HEAD_15_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_HEAD_15_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_HEAD_15_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_HEAD_15_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_HEAD_15_RESERVED_0_MASK) >> HWSCH_CMD_RING_HEAD_15_RESERVED_0_LSB)
#define HWSCH_CMD_RING_HEAD_15_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_15_RESERVED_0_LSB) & HWSCH_CMD_RING_HEAD_15_RESERVED_0_MASK)
#define HWSCH_CMD_RING_HEAD_15_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_HEAD_15_HWSCH_CMD_RING_HEAD_DATA_MSB          15
#define HWSCH_CMD_RING_HEAD_15_HWSCH_CMD_RING_HEAD_DATA_LSB          0
#define HWSCH_CMD_RING_HEAD_15_HWSCH_CMD_RING_HEAD_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_HEAD_15_HWSCH_CMD_RING_HEAD_DATA_GET(x)       (((x) & HWSCH_CMD_RING_HEAD_15_HWSCH_CMD_RING_HEAD_DATA_MASK) >> HWSCH_CMD_RING_HEAD_15_HWSCH_CMD_RING_HEAD_DATA_LSB)
#define HWSCH_CMD_RING_HEAD_15_HWSCH_CMD_RING_HEAD_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_HEAD_15_HWSCH_CMD_RING_HEAD_DATA_LSB) & HWSCH_CMD_RING_HEAD_15_HWSCH_CMD_RING_HEAD_DATA_MASK)
#define HWSCH_CMD_RING_HEAD_15_HWSCH_CMD_RING_HEAD_DATA_RESET        0
#define HWSCH_CMD_RING_HEAD_15_ADDRESS                               0x0001d8
#define HWSCH_CMD_RING_HEAD_15_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_15_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_HEAD_15_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_HEAD_15_RESET                                 0x00000000

// 0x01dc (HWSCH_CMD_RING_TAIL_0)
#define HWSCH_CMD_RING_TAIL_0_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_TAIL_0_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_TAIL_0_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_TAIL_0_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_TAIL_0_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_0_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_0_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_0_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_0_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_0_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_TAIL_0_HWSCH_CMD_RING_TAIL_DATA_MSB           15
#define HWSCH_CMD_RING_TAIL_0_HWSCH_CMD_RING_TAIL_DATA_LSB           0
#define HWSCH_CMD_RING_TAIL_0_HWSCH_CMD_RING_TAIL_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_TAIL_0_HWSCH_CMD_RING_TAIL_DATA_GET(x)        (((x) & HWSCH_CMD_RING_TAIL_0_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_0_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_0_HWSCH_CMD_RING_TAIL_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_0_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_0_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_0_HWSCH_CMD_RING_TAIL_DATA_RESET         0
#define HWSCH_CMD_RING_TAIL_0_ADDRESS                                0x0001dc
#define HWSCH_CMD_RING_TAIL_0_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_0_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_0_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_TAIL_0_RESET                                  0x00000000

// 0x01e0 (HWSCH_CMD_RING_TAIL_1)
#define HWSCH_CMD_RING_TAIL_1_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_TAIL_1_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_TAIL_1_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_TAIL_1_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_TAIL_1_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_1_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_1_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_1_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_1_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_1_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_TAIL_1_HWSCH_CMD_RING_TAIL_DATA_MSB           15
#define HWSCH_CMD_RING_TAIL_1_HWSCH_CMD_RING_TAIL_DATA_LSB           0
#define HWSCH_CMD_RING_TAIL_1_HWSCH_CMD_RING_TAIL_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_TAIL_1_HWSCH_CMD_RING_TAIL_DATA_GET(x)        (((x) & HWSCH_CMD_RING_TAIL_1_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_1_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_1_HWSCH_CMD_RING_TAIL_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_1_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_1_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_1_HWSCH_CMD_RING_TAIL_DATA_RESET         0
#define HWSCH_CMD_RING_TAIL_1_ADDRESS                                0x0001e0
#define HWSCH_CMD_RING_TAIL_1_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_1_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_1_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_TAIL_1_RESET                                  0x00000000

// 0x01e4 (HWSCH_CMD_RING_TAIL_2)
#define HWSCH_CMD_RING_TAIL_2_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_TAIL_2_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_TAIL_2_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_TAIL_2_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_TAIL_2_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_2_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_2_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_2_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_2_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_2_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_TAIL_2_HWSCH_CMD_RING_TAIL_DATA_MSB           15
#define HWSCH_CMD_RING_TAIL_2_HWSCH_CMD_RING_TAIL_DATA_LSB           0
#define HWSCH_CMD_RING_TAIL_2_HWSCH_CMD_RING_TAIL_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_TAIL_2_HWSCH_CMD_RING_TAIL_DATA_GET(x)        (((x) & HWSCH_CMD_RING_TAIL_2_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_2_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_2_HWSCH_CMD_RING_TAIL_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_2_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_2_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_2_HWSCH_CMD_RING_TAIL_DATA_RESET         0
#define HWSCH_CMD_RING_TAIL_2_ADDRESS                                0x0001e4
#define HWSCH_CMD_RING_TAIL_2_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_2_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_2_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_TAIL_2_RESET                                  0x00000000

// 0x01e8 (HWSCH_CMD_RING_TAIL_3)
#define HWSCH_CMD_RING_TAIL_3_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_TAIL_3_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_TAIL_3_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_TAIL_3_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_TAIL_3_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_3_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_3_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_3_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_3_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_3_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_TAIL_3_HWSCH_CMD_RING_TAIL_DATA_MSB           15
#define HWSCH_CMD_RING_TAIL_3_HWSCH_CMD_RING_TAIL_DATA_LSB           0
#define HWSCH_CMD_RING_TAIL_3_HWSCH_CMD_RING_TAIL_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_TAIL_3_HWSCH_CMD_RING_TAIL_DATA_GET(x)        (((x) & HWSCH_CMD_RING_TAIL_3_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_3_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_3_HWSCH_CMD_RING_TAIL_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_3_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_3_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_3_HWSCH_CMD_RING_TAIL_DATA_RESET         0
#define HWSCH_CMD_RING_TAIL_3_ADDRESS                                0x0001e8
#define HWSCH_CMD_RING_TAIL_3_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_3_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_3_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_TAIL_3_RESET                                  0x00000000

// 0x01ec (HWSCH_CMD_RING_TAIL_4)
#define HWSCH_CMD_RING_TAIL_4_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_TAIL_4_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_TAIL_4_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_TAIL_4_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_TAIL_4_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_4_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_4_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_4_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_4_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_4_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_TAIL_4_HWSCH_CMD_RING_TAIL_DATA_MSB           15
#define HWSCH_CMD_RING_TAIL_4_HWSCH_CMD_RING_TAIL_DATA_LSB           0
#define HWSCH_CMD_RING_TAIL_4_HWSCH_CMD_RING_TAIL_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_TAIL_4_HWSCH_CMD_RING_TAIL_DATA_GET(x)        (((x) & HWSCH_CMD_RING_TAIL_4_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_4_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_4_HWSCH_CMD_RING_TAIL_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_4_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_4_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_4_HWSCH_CMD_RING_TAIL_DATA_RESET         0
#define HWSCH_CMD_RING_TAIL_4_ADDRESS                                0x0001ec
#define HWSCH_CMD_RING_TAIL_4_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_4_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_4_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_TAIL_4_RESET                                  0x00000000

// 0x01f0 (HWSCH_CMD_RING_TAIL_5)
#define HWSCH_CMD_RING_TAIL_5_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_TAIL_5_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_TAIL_5_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_TAIL_5_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_TAIL_5_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_5_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_5_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_5_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_5_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_5_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_TAIL_5_HWSCH_CMD_RING_TAIL_DATA_MSB           15
#define HWSCH_CMD_RING_TAIL_5_HWSCH_CMD_RING_TAIL_DATA_LSB           0
#define HWSCH_CMD_RING_TAIL_5_HWSCH_CMD_RING_TAIL_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_TAIL_5_HWSCH_CMD_RING_TAIL_DATA_GET(x)        (((x) & HWSCH_CMD_RING_TAIL_5_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_5_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_5_HWSCH_CMD_RING_TAIL_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_5_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_5_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_5_HWSCH_CMD_RING_TAIL_DATA_RESET         0
#define HWSCH_CMD_RING_TAIL_5_ADDRESS                                0x0001f0
#define HWSCH_CMD_RING_TAIL_5_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_5_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_5_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_TAIL_5_RESET                                  0x00000000

// 0x01f4 (HWSCH_CMD_RING_TAIL_6)
#define HWSCH_CMD_RING_TAIL_6_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_TAIL_6_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_TAIL_6_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_TAIL_6_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_TAIL_6_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_6_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_6_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_6_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_6_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_6_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_TAIL_6_HWSCH_CMD_RING_TAIL_DATA_MSB           15
#define HWSCH_CMD_RING_TAIL_6_HWSCH_CMD_RING_TAIL_DATA_LSB           0
#define HWSCH_CMD_RING_TAIL_6_HWSCH_CMD_RING_TAIL_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_TAIL_6_HWSCH_CMD_RING_TAIL_DATA_GET(x)        (((x) & HWSCH_CMD_RING_TAIL_6_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_6_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_6_HWSCH_CMD_RING_TAIL_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_6_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_6_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_6_HWSCH_CMD_RING_TAIL_DATA_RESET         0
#define HWSCH_CMD_RING_TAIL_6_ADDRESS                                0x0001f4
#define HWSCH_CMD_RING_TAIL_6_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_6_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_6_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_TAIL_6_RESET                                  0x00000000

// 0x01f8 (HWSCH_CMD_RING_TAIL_7)
#define HWSCH_CMD_RING_TAIL_7_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_TAIL_7_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_TAIL_7_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_TAIL_7_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_TAIL_7_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_7_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_7_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_7_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_7_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_7_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_TAIL_7_HWSCH_CMD_RING_TAIL_DATA_MSB           15
#define HWSCH_CMD_RING_TAIL_7_HWSCH_CMD_RING_TAIL_DATA_LSB           0
#define HWSCH_CMD_RING_TAIL_7_HWSCH_CMD_RING_TAIL_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_TAIL_7_HWSCH_CMD_RING_TAIL_DATA_GET(x)        (((x) & HWSCH_CMD_RING_TAIL_7_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_7_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_7_HWSCH_CMD_RING_TAIL_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_7_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_7_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_7_HWSCH_CMD_RING_TAIL_DATA_RESET         0
#define HWSCH_CMD_RING_TAIL_7_ADDRESS                                0x0001f8
#define HWSCH_CMD_RING_TAIL_7_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_7_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_7_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_TAIL_7_RESET                                  0x00000000

// 0x01fc (HWSCH_CMD_RING_TAIL_8)
#define HWSCH_CMD_RING_TAIL_8_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_TAIL_8_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_TAIL_8_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_TAIL_8_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_TAIL_8_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_8_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_8_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_8_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_8_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_8_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_TAIL_8_HWSCH_CMD_RING_TAIL_DATA_MSB           15
#define HWSCH_CMD_RING_TAIL_8_HWSCH_CMD_RING_TAIL_DATA_LSB           0
#define HWSCH_CMD_RING_TAIL_8_HWSCH_CMD_RING_TAIL_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_TAIL_8_HWSCH_CMD_RING_TAIL_DATA_GET(x)        (((x) & HWSCH_CMD_RING_TAIL_8_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_8_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_8_HWSCH_CMD_RING_TAIL_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_8_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_8_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_8_HWSCH_CMD_RING_TAIL_DATA_RESET         0
#define HWSCH_CMD_RING_TAIL_8_ADDRESS                                0x0001fc
#define HWSCH_CMD_RING_TAIL_8_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_8_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_8_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_TAIL_8_RESET                                  0x00000000

// 0x0200 (HWSCH_CMD_RING_TAIL_9)
#define HWSCH_CMD_RING_TAIL_9_RESERVED_0_MSB                         31
#define HWSCH_CMD_RING_TAIL_9_RESERVED_0_LSB                         16
#define HWSCH_CMD_RING_TAIL_9_RESERVED_0_MASK                        0xffff0000
#define HWSCH_CMD_RING_TAIL_9_RESERVED_0_GET(x)                      (((x) & HWSCH_CMD_RING_TAIL_9_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_9_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_9_RESERVED_0_SET(x)                      (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_9_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_9_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_9_RESERVED_0_RESET                       0
#define HWSCH_CMD_RING_TAIL_9_HWSCH_CMD_RING_TAIL_DATA_MSB           15
#define HWSCH_CMD_RING_TAIL_9_HWSCH_CMD_RING_TAIL_DATA_LSB           0
#define HWSCH_CMD_RING_TAIL_9_HWSCH_CMD_RING_TAIL_DATA_MASK          0x0000ffff
#define HWSCH_CMD_RING_TAIL_9_HWSCH_CMD_RING_TAIL_DATA_GET(x)        (((x) & HWSCH_CMD_RING_TAIL_9_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_9_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_9_HWSCH_CMD_RING_TAIL_DATA_SET(x)        (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_9_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_9_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_9_HWSCH_CMD_RING_TAIL_DATA_RESET         0
#define HWSCH_CMD_RING_TAIL_9_ADDRESS                                0x000200
#define HWSCH_CMD_RING_TAIL_9_HW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_9_SW_MASK                                0xffffffff
#define HWSCH_CMD_RING_TAIL_9_RSTMASK                                0x00000000
#define HWSCH_CMD_RING_TAIL_9_RESET                                  0x00000000

// 0x0204 (HWSCH_CMD_RING_TAIL_10)
#define HWSCH_CMD_RING_TAIL_10_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_TAIL_10_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_TAIL_10_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_TAIL_10_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_TAIL_10_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_10_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_10_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_10_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_10_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_10_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_TAIL_10_HWSCH_CMD_RING_TAIL_DATA_MSB          15
#define HWSCH_CMD_RING_TAIL_10_HWSCH_CMD_RING_TAIL_DATA_LSB          0
#define HWSCH_CMD_RING_TAIL_10_HWSCH_CMD_RING_TAIL_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_TAIL_10_HWSCH_CMD_RING_TAIL_DATA_GET(x)       (((x) & HWSCH_CMD_RING_TAIL_10_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_10_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_10_HWSCH_CMD_RING_TAIL_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_10_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_10_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_10_HWSCH_CMD_RING_TAIL_DATA_RESET        0
#define HWSCH_CMD_RING_TAIL_10_ADDRESS                               0x000204
#define HWSCH_CMD_RING_TAIL_10_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_10_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_10_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_TAIL_10_RESET                                 0x00000000

// 0x0208 (HWSCH_CMD_RING_TAIL_11)
#define HWSCH_CMD_RING_TAIL_11_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_TAIL_11_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_TAIL_11_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_TAIL_11_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_TAIL_11_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_11_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_11_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_11_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_11_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_11_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_TAIL_11_HWSCH_CMD_RING_TAIL_DATA_MSB          15
#define HWSCH_CMD_RING_TAIL_11_HWSCH_CMD_RING_TAIL_DATA_LSB          0
#define HWSCH_CMD_RING_TAIL_11_HWSCH_CMD_RING_TAIL_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_TAIL_11_HWSCH_CMD_RING_TAIL_DATA_GET(x)       (((x) & HWSCH_CMD_RING_TAIL_11_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_11_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_11_HWSCH_CMD_RING_TAIL_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_11_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_11_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_11_HWSCH_CMD_RING_TAIL_DATA_RESET        0
#define HWSCH_CMD_RING_TAIL_11_ADDRESS                               0x000208
#define HWSCH_CMD_RING_TAIL_11_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_11_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_11_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_TAIL_11_RESET                                 0x00000000

// 0x020c (HWSCH_CMD_RING_TAIL_12)
#define HWSCH_CMD_RING_TAIL_12_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_TAIL_12_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_TAIL_12_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_TAIL_12_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_TAIL_12_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_12_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_12_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_12_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_12_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_12_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_TAIL_12_HWSCH_CMD_RING_TAIL_DATA_MSB          15
#define HWSCH_CMD_RING_TAIL_12_HWSCH_CMD_RING_TAIL_DATA_LSB          0
#define HWSCH_CMD_RING_TAIL_12_HWSCH_CMD_RING_TAIL_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_TAIL_12_HWSCH_CMD_RING_TAIL_DATA_GET(x)       (((x) & HWSCH_CMD_RING_TAIL_12_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_12_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_12_HWSCH_CMD_RING_TAIL_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_12_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_12_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_12_HWSCH_CMD_RING_TAIL_DATA_RESET        0
#define HWSCH_CMD_RING_TAIL_12_ADDRESS                               0x00020c
#define HWSCH_CMD_RING_TAIL_12_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_12_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_12_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_TAIL_12_RESET                                 0x00000000

// 0x0210 (HWSCH_CMD_RING_TAIL_13)
#define HWSCH_CMD_RING_TAIL_13_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_TAIL_13_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_TAIL_13_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_TAIL_13_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_TAIL_13_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_13_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_13_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_13_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_13_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_13_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_TAIL_13_HWSCH_CMD_RING_TAIL_DATA_MSB          15
#define HWSCH_CMD_RING_TAIL_13_HWSCH_CMD_RING_TAIL_DATA_LSB          0
#define HWSCH_CMD_RING_TAIL_13_HWSCH_CMD_RING_TAIL_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_TAIL_13_HWSCH_CMD_RING_TAIL_DATA_GET(x)       (((x) & HWSCH_CMD_RING_TAIL_13_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_13_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_13_HWSCH_CMD_RING_TAIL_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_13_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_13_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_13_HWSCH_CMD_RING_TAIL_DATA_RESET        0
#define HWSCH_CMD_RING_TAIL_13_ADDRESS                               0x000210
#define HWSCH_CMD_RING_TAIL_13_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_13_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_13_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_TAIL_13_RESET                                 0x00000000

// 0x0214 (HWSCH_CMD_RING_TAIL_14)
#define HWSCH_CMD_RING_TAIL_14_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_TAIL_14_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_TAIL_14_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_TAIL_14_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_TAIL_14_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_14_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_14_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_14_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_14_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_14_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_TAIL_14_HWSCH_CMD_RING_TAIL_DATA_MSB          15
#define HWSCH_CMD_RING_TAIL_14_HWSCH_CMD_RING_TAIL_DATA_LSB          0
#define HWSCH_CMD_RING_TAIL_14_HWSCH_CMD_RING_TAIL_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_TAIL_14_HWSCH_CMD_RING_TAIL_DATA_GET(x)       (((x) & HWSCH_CMD_RING_TAIL_14_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_14_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_14_HWSCH_CMD_RING_TAIL_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_14_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_14_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_14_HWSCH_CMD_RING_TAIL_DATA_RESET        0
#define HWSCH_CMD_RING_TAIL_14_ADDRESS                               0x000214
#define HWSCH_CMD_RING_TAIL_14_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_14_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_14_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_TAIL_14_RESET                                 0x00000000

// 0x0218 (HWSCH_CMD_RING_TAIL_15)
#define HWSCH_CMD_RING_TAIL_15_RESERVED_0_MSB                        31
#define HWSCH_CMD_RING_TAIL_15_RESERVED_0_LSB                        16
#define HWSCH_CMD_RING_TAIL_15_RESERVED_0_MASK                       0xffff0000
#define HWSCH_CMD_RING_TAIL_15_RESERVED_0_GET(x)                     (((x) & HWSCH_CMD_RING_TAIL_15_RESERVED_0_MASK) >> HWSCH_CMD_RING_TAIL_15_RESERVED_0_LSB)
#define HWSCH_CMD_RING_TAIL_15_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_15_RESERVED_0_LSB) & HWSCH_CMD_RING_TAIL_15_RESERVED_0_MASK)
#define HWSCH_CMD_RING_TAIL_15_RESERVED_0_RESET                      0
#define HWSCH_CMD_RING_TAIL_15_HWSCH_CMD_RING_TAIL_DATA_MSB          15
#define HWSCH_CMD_RING_TAIL_15_HWSCH_CMD_RING_TAIL_DATA_LSB          0
#define HWSCH_CMD_RING_TAIL_15_HWSCH_CMD_RING_TAIL_DATA_MASK         0x0000ffff
#define HWSCH_CMD_RING_TAIL_15_HWSCH_CMD_RING_TAIL_DATA_GET(x)       (((x) & HWSCH_CMD_RING_TAIL_15_HWSCH_CMD_RING_TAIL_DATA_MASK) >> HWSCH_CMD_RING_TAIL_15_HWSCH_CMD_RING_TAIL_DATA_LSB)
#define HWSCH_CMD_RING_TAIL_15_HWSCH_CMD_RING_TAIL_DATA_SET(x)       (((0x0 | (x)) << HWSCH_CMD_RING_TAIL_15_HWSCH_CMD_RING_TAIL_DATA_LSB) & HWSCH_CMD_RING_TAIL_15_HWSCH_CMD_RING_TAIL_DATA_MASK)
#define HWSCH_CMD_RING_TAIL_15_HWSCH_CMD_RING_TAIL_DATA_RESET        0
#define HWSCH_CMD_RING_TAIL_15_ADDRESS                               0x000218
#define HWSCH_CMD_RING_TAIL_15_HW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_15_SW_MASK                               0xffffffff
#define HWSCH_CMD_RING_TAIL_15_RSTMASK                               0x00000000
#define HWSCH_CMD_RING_TAIL_15_RESET                                 0x00000000

// 0x021c (HWSCH_CMD_RING_THRESHOLD_0)
#define HWSCH_CMD_RING_THRESHOLD_0_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_THRESHOLD_0_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_THRESHOLD_0_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_0_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_THRESHOLD_0_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_0_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_0_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_0_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_0_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_0_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_THRESHOLD_0_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_0_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_0_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_0_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_0_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_0_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_0_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_0_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_0_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_0_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_0_ADDRESS                           0x00021c
#define HWSCH_CMD_RING_THRESHOLD_0_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_0_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_0_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_0_RESET                             0x000000f0

// 0x0220 (HWSCH_CMD_RING_THRESHOLD_1)
#define HWSCH_CMD_RING_THRESHOLD_1_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_THRESHOLD_1_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_THRESHOLD_1_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_1_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_THRESHOLD_1_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_1_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_1_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_1_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_1_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_1_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_THRESHOLD_1_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_1_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_1_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_1_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_1_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_1_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_1_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_1_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_1_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_1_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_1_ADDRESS                           0x000220
#define HWSCH_CMD_RING_THRESHOLD_1_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_1_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_1_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_1_RESET                             0x000000f0

// 0x0224 (HWSCH_CMD_RING_THRESHOLD_2)
#define HWSCH_CMD_RING_THRESHOLD_2_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_THRESHOLD_2_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_THRESHOLD_2_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_2_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_THRESHOLD_2_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_2_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_2_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_2_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_2_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_2_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_THRESHOLD_2_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_2_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_2_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_2_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_2_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_2_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_2_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_2_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_2_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_2_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_2_ADDRESS                           0x000224
#define HWSCH_CMD_RING_THRESHOLD_2_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_2_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_2_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_2_RESET                             0x000000f0

// 0x0228 (HWSCH_CMD_RING_THRESHOLD_3)
#define HWSCH_CMD_RING_THRESHOLD_3_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_THRESHOLD_3_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_THRESHOLD_3_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_3_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_THRESHOLD_3_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_3_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_3_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_3_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_3_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_3_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_THRESHOLD_3_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_3_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_3_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_3_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_3_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_3_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_3_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_3_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_3_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_3_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_3_ADDRESS                           0x000228
#define HWSCH_CMD_RING_THRESHOLD_3_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_3_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_3_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_3_RESET                             0x000000f0

// 0x022c (HWSCH_CMD_RING_THRESHOLD_4)
#define HWSCH_CMD_RING_THRESHOLD_4_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_THRESHOLD_4_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_THRESHOLD_4_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_4_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_THRESHOLD_4_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_4_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_4_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_4_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_4_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_4_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_THRESHOLD_4_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_4_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_4_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_4_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_4_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_4_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_4_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_4_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_4_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_4_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_4_ADDRESS                           0x00022c
#define HWSCH_CMD_RING_THRESHOLD_4_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_4_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_4_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_4_RESET                             0x000000f0

// 0x0230 (HWSCH_CMD_RING_THRESHOLD_5)
#define HWSCH_CMD_RING_THRESHOLD_5_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_THRESHOLD_5_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_THRESHOLD_5_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_5_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_THRESHOLD_5_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_5_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_5_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_5_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_5_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_5_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_THRESHOLD_5_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_5_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_5_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_5_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_5_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_5_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_5_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_5_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_5_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_5_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_5_ADDRESS                           0x000230
#define HWSCH_CMD_RING_THRESHOLD_5_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_5_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_5_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_5_RESET                             0x000000f0

// 0x0234 (HWSCH_CMD_RING_THRESHOLD_6)
#define HWSCH_CMD_RING_THRESHOLD_6_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_THRESHOLD_6_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_THRESHOLD_6_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_6_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_THRESHOLD_6_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_6_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_6_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_6_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_6_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_6_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_THRESHOLD_6_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_6_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_6_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_6_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_6_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_6_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_6_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_6_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_6_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_6_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_6_ADDRESS                           0x000234
#define HWSCH_CMD_RING_THRESHOLD_6_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_6_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_6_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_6_RESET                             0x000000f0

// 0x0238 (HWSCH_CMD_RING_THRESHOLD_7)
#define HWSCH_CMD_RING_THRESHOLD_7_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_THRESHOLD_7_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_THRESHOLD_7_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_7_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_THRESHOLD_7_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_7_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_7_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_7_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_7_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_7_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_THRESHOLD_7_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_7_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_7_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_7_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_7_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_7_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_7_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_7_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_7_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_7_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_7_ADDRESS                           0x000238
#define HWSCH_CMD_RING_THRESHOLD_7_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_7_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_7_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_7_RESET                             0x000000f0

// 0x023c (HWSCH_CMD_RING_THRESHOLD_8)
#define HWSCH_CMD_RING_THRESHOLD_8_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_THRESHOLD_8_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_THRESHOLD_8_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_8_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_THRESHOLD_8_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_8_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_8_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_8_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_8_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_8_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_THRESHOLD_8_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_8_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_8_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_8_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_8_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_8_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_8_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_8_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_8_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_8_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_8_ADDRESS                           0x00023c
#define HWSCH_CMD_RING_THRESHOLD_8_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_8_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_8_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_8_RESET                             0x000000f0

// 0x0240 (HWSCH_CMD_RING_THRESHOLD_9)
#define HWSCH_CMD_RING_THRESHOLD_9_RESERVED_0_MSB                    31
#define HWSCH_CMD_RING_THRESHOLD_9_RESERVED_0_LSB                    16
#define HWSCH_CMD_RING_THRESHOLD_9_RESERVED_0_MASK                   0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_9_RESERVED_0_GET(x)                 (((x) & HWSCH_CMD_RING_THRESHOLD_9_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_9_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_9_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_9_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_9_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_9_RESERVED_0_RESET                  0
#define HWSCH_CMD_RING_THRESHOLD_9_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_9_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_9_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_9_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_9_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_9_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_9_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_9_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_9_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_9_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_9_ADDRESS                           0x000240
#define HWSCH_CMD_RING_THRESHOLD_9_HW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_9_SW_MASK                           0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_9_RSTMASK                           0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_9_RESET                             0x000000f0

// 0x0244 (HWSCH_CMD_RING_THRESHOLD_10)
#define HWSCH_CMD_RING_THRESHOLD_10_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_THRESHOLD_10_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_THRESHOLD_10_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_10_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_THRESHOLD_10_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_10_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_10_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_10_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_10_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_10_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_THRESHOLD_10_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_10_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_10_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_10_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_10_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_10_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_10_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_10_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_10_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_10_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_10_ADDRESS                          0x000244
#define HWSCH_CMD_RING_THRESHOLD_10_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_10_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_10_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_10_RESET                            0x000000f0

// 0x0248 (HWSCH_CMD_RING_THRESHOLD_11)
#define HWSCH_CMD_RING_THRESHOLD_11_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_THRESHOLD_11_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_THRESHOLD_11_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_11_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_THRESHOLD_11_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_11_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_11_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_11_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_11_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_11_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_THRESHOLD_11_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_11_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_11_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_11_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_11_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_11_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_11_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_11_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_11_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_11_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_11_ADDRESS                          0x000248
#define HWSCH_CMD_RING_THRESHOLD_11_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_11_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_11_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_11_RESET                            0x000000f0

// 0x024c (HWSCH_CMD_RING_THRESHOLD_12)
#define HWSCH_CMD_RING_THRESHOLD_12_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_THRESHOLD_12_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_THRESHOLD_12_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_12_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_THRESHOLD_12_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_12_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_12_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_12_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_12_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_12_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_THRESHOLD_12_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_12_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_12_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_12_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_12_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_12_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_12_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_12_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_12_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_12_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_12_ADDRESS                          0x00024c
#define HWSCH_CMD_RING_THRESHOLD_12_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_12_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_12_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_12_RESET                            0x000000f0

// 0x0250 (HWSCH_CMD_RING_THRESHOLD_13)
#define HWSCH_CMD_RING_THRESHOLD_13_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_THRESHOLD_13_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_THRESHOLD_13_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_13_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_THRESHOLD_13_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_13_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_13_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_13_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_13_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_13_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_THRESHOLD_13_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_13_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_13_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_13_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_13_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_13_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_13_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_13_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_13_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_13_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_13_ADDRESS                          0x000250
#define HWSCH_CMD_RING_THRESHOLD_13_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_13_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_13_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_13_RESET                            0x000000f0

// 0x0254 (HWSCH_CMD_RING_THRESHOLD_14)
#define HWSCH_CMD_RING_THRESHOLD_14_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_THRESHOLD_14_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_THRESHOLD_14_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_14_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_THRESHOLD_14_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_14_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_14_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_14_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_14_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_14_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_THRESHOLD_14_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_14_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_14_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_14_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_14_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_14_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_14_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_14_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_14_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_14_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_14_ADDRESS                          0x000254
#define HWSCH_CMD_RING_THRESHOLD_14_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_14_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_14_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_14_RESET                            0x000000f0

// 0x0258 (HWSCH_CMD_RING_THRESHOLD_15)
#define HWSCH_CMD_RING_THRESHOLD_15_RESERVED_0_MSB                   31
#define HWSCH_CMD_RING_THRESHOLD_15_RESERVED_0_LSB                   16
#define HWSCH_CMD_RING_THRESHOLD_15_RESERVED_0_MASK                  0xffff0000
#define HWSCH_CMD_RING_THRESHOLD_15_RESERVED_0_GET(x)                (((x) & HWSCH_CMD_RING_THRESHOLD_15_RESERVED_0_MASK) >> HWSCH_CMD_RING_THRESHOLD_15_RESERVED_0_LSB)
#define HWSCH_CMD_RING_THRESHOLD_15_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_15_RESERVED_0_LSB) & HWSCH_CMD_RING_THRESHOLD_15_RESERVED_0_MASK)
#define HWSCH_CMD_RING_THRESHOLD_15_RESERVED_0_RESET                 0
#define HWSCH_CMD_RING_THRESHOLD_15_HWSCH_CMD_RING_THRESHOLD_DATA_MSB 15
#define HWSCH_CMD_RING_THRESHOLD_15_HWSCH_CMD_RING_THRESHOLD_DATA_LSB 0
#define HWSCH_CMD_RING_THRESHOLD_15_HWSCH_CMD_RING_THRESHOLD_DATA_MASK 0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_15_HWSCH_CMD_RING_THRESHOLD_DATA_GET(x) (((x) & HWSCH_CMD_RING_THRESHOLD_15_HWSCH_CMD_RING_THRESHOLD_DATA_MASK) >> HWSCH_CMD_RING_THRESHOLD_15_HWSCH_CMD_RING_THRESHOLD_DATA_LSB)
#define HWSCH_CMD_RING_THRESHOLD_15_HWSCH_CMD_RING_THRESHOLD_DATA_SET(x) (((0x0 | (x)) << HWSCH_CMD_RING_THRESHOLD_15_HWSCH_CMD_RING_THRESHOLD_DATA_LSB) & HWSCH_CMD_RING_THRESHOLD_15_HWSCH_CMD_RING_THRESHOLD_DATA_MASK)
#define HWSCH_CMD_RING_THRESHOLD_15_HWSCH_CMD_RING_THRESHOLD_DATA_RESET 240
#define HWSCH_CMD_RING_THRESHOLD_15_ADDRESS                          0x000258
#define HWSCH_CMD_RING_THRESHOLD_15_HW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_15_SW_MASK                          0xffffffff
#define HWSCH_CMD_RING_THRESHOLD_15_RSTMASK                          0x0000ffff
#define HWSCH_CMD_RING_THRESHOLD_15_RESET                            0x000000f0

// 0x025c (HWSCH_STATUS_BASE)
#define HWSCH_STATUS_BASE_HWSCH_STATUS_BASE_DATA_MSB                 31
#define HWSCH_STATUS_BASE_HWSCH_STATUS_BASE_DATA_LSB                 0
#define HWSCH_STATUS_BASE_HWSCH_STATUS_BASE_DATA_MASK                0xffffffff
#define HWSCH_STATUS_BASE_HWSCH_STATUS_BASE_DATA_GET(x)              (((x) & HWSCH_STATUS_BASE_HWSCH_STATUS_BASE_DATA_MASK) >> HWSCH_STATUS_BASE_HWSCH_STATUS_BASE_DATA_LSB)
#define HWSCH_STATUS_BASE_HWSCH_STATUS_BASE_DATA_SET(x)              (((0x0 | (x)) << HWSCH_STATUS_BASE_HWSCH_STATUS_BASE_DATA_LSB) & HWSCH_STATUS_BASE_HWSCH_STATUS_BASE_DATA_MASK)
#define HWSCH_STATUS_BASE_HWSCH_STATUS_BASE_DATA_RESET               0
#define HWSCH_STATUS_BASE_ADDRESS                                    0x00025c
#define HWSCH_STATUS_BASE_HW_MASK                                    0xffffffff
#define HWSCH_STATUS_BASE_SW_MASK                                    0xffffffff
#define HWSCH_STATUS_BASE_RSTMASK                                    0x00000000
#define HWSCH_STATUS_BASE_RESET                                      0x00000000

// 0x0260 (HWSCH_STATUS_NUM_ENTRY)
#define HWSCH_STATUS_NUM_ENTRY_RESERVED_0_MSB                        31
#define HWSCH_STATUS_NUM_ENTRY_RESERVED_0_LSB                        16
#define HWSCH_STATUS_NUM_ENTRY_RESERVED_0_MASK                       0xffff0000
#define HWSCH_STATUS_NUM_ENTRY_RESERVED_0_GET(x)                     (((x) & HWSCH_STATUS_NUM_ENTRY_RESERVED_0_MASK) >> HWSCH_STATUS_NUM_ENTRY_RESERVED_0_LSB)
#define HWSCH_STATUS_NUM_ENTRY_RESERVED_0_SET(x)                     (((0x0 | (x)) << HWSCH_STATUS_NUM_ENTRY_RESERVED_0_LSB) & HWSCH_STATUS_NUM_ENTRY_RESERVED_0_MASK)
#define HWSCH_STATUS_NUM_ENTRY_RESERVED_0_RESET                      0
#define HWSCH_STATUS_NUM_ENTRY_HWSCH_STATUS_NUM_ENTRY_DATA_MSB       15
#define HWSCH_STATUS_NUM_ENTRY_HWSCH_STATUS_NUM_ENTRY_DATA_LSB       0
#define HWSCH_STATUS_NUM_ENTRY_HWSCH_STATUS_NUM_ENTRY_DATA_MASK      0x0000ffff
#define HWSCH_STATUS_NUM_ENTRY_HWSCH_STATUS_NUM_ENTRY_DATA_GET(x)    (((x) & HWSCH_STATUS_NUM_ENTRY_HWSCH_STATUS_NUM_ENTRY_DATA_MASK) >> HWSCH_STATUS_NUM_ENTRY_HWSCH_STATUS_NUM_ENTRY_DATA_LSB)
#define HWSCH_STATUS_NUM_ENTRY_HWSCH_STATUS_NUM_ENTRY_DATA_SET(x)    (((0x0 | (x)) << HWSCH_STATUS_NUM_ENTRY_HWSCH_STATUS_NUM_ENTRY_DATA_LSB) & HWSCH_STATUS_NUM_ENTRY_HWSCH_STATUS_NUM_ENTRY_DATA_MASK)
#define HWSCH_STATUS_NUM_ENTRY_HWSCH_STATUS_NUM_ENTRY_DATA_RESET     15
#define HWSCH_STATUS_NUM_ENTRY_ADDRESS                               0x000260
#define HWSCH_STATUS_NUM_ENTRY_HW_MASK                               0xffffffff
#define HWSCH_STATUS_NUM_ENTRY_SW_MASK                               0xffffffff
#define HWSCH_STATUS_NUM_ENTRY_RSTMASK                               0x0000ffff
#define HWSCH_STATUS_NUM_ENTRY_RESET                                 0x0000000f

// 0x0264 (HWSCH_STATUS_HEAD)
#define HWSCH_STATUS_HEAD_RESERVED_0_MSB                             31
#define HWSCH_STATUS_HEAD_RESERVED_0_LSB                             16
#define HWSCH_STATUS_HEAD_RESERVED_0_MASK                            0xffff0000
#define HWSCH_STATUS_HEAD_RESERVED_0_GET(x)                          (((x) & HWSCH_STATUS_HEAD_RESERVED_0_MASK) >> HWSCH_STATUS_HEAD_RESERVED_0_LSB)
#define HWSCH_STATUS_HEAD_RESERVED_0_SET(x)                          (((0x0 | (x)) << HWSCH_STATUS_HEAD_RESERVED_0_LSB) & HWSCH_STATUS_HEAD_RESERVED_0_MASK)
#define HWSCH_STATUS_HEAD_RESERVED_0_RESET                           0
#define HWSCH_STATUS_HEAD_HWSCH_STATUS_HEAD_DATA_MSB                 15
#define HWSCH_STATUS_HEAD_HWSCH_STATUS_HEAD_DATA_LSB                 0
#define HWSCH_STATUS_HEAD_HWSCH_STATUS_HEAD_DATA_MASK                0x0000ffff
#define HWSCH_STATUS_HEAD_HWSCH_STATUS_HEAD_DATA_GET(x)              (((x) & HWSCH_STATUS_HEAD_HWSCH_STATUS_HEAD_DATA_MASK) >> HWSCH_STATUS_HEAD_HWSCH_STATUS_HEAD_DATA_LSB)
#define HWSCH_STATUS_HEAD_HWSCH_STATUS_HEAD_DATA_SET(x)              (((0x0 | (x)) << HWSCH_STATUS_HEAD_HWSCH_STATUS_HEAD_DATA_LSB) & HWSCH_STATUS_HEAD_HWSCH_STATUS_HEAD_DATA_MASK)
#define HWSCH_STATUS_HEAD_HWSCH_STATUS_HEAD_DATA_RESET               0
#define HWSCH_STATUS_HEAD_ADDRESS                                    0x000264
#define HWSCH_STATUS_HEAD_HW_MASK                                    0xffffffff
#define HWSCH_STATUS_HEAD_SW_MASK                                    0xffffffff
#define HWSCH_STATUS_HEAD_RSTMASK                                    0x00000000
#define HWSCH_STATUS_HEAD_RESET                                      0x00000000

// 0x0268 (HWSCH_STATUS_TAIL)
#define HWSCH_STATUS_TAIL_RESERVED_0_MSB                             31
#define HWSCH_STATUS_TAIL_RESERVED_0_LSB                             16
#define HWSCH_STATUS_TAIL_RESERVED_0_MASK                            0xffff0000
#define HWSCH_STATUS_TAIL_RESERVED_0_GET(x)                          (((x) & HWSCH_STATUS_TAIL_RESERVED_0_MASK) >> HWSCH_STATUS_TAIL_RESERVED_0_LSB)
#define HWSCH_STATUS_TAIL_RESERVED_0_SET(x)                          (((0x0 | (x)) << HWSCH_STATUS_TAIL_RESERVED_0_LSB) & HWSCH_STATUS_TAIL_RESERVED_0_MASK)
#define HWSCH_STATUS_TAIL_RESERVED_0_RESET                           0
#define HWSCH_STATUS_TAIL_HWSCH_STATUS_TAIL_DATA_MSB                 15
#define HWSCH_STATUS_TAIL_HWSCH_STATUS_TAIL_DATA_LSB                 0
#define HWSCH_STATUS_TAIL_HWSCH_STATUS_TAIL_DATA_MASK                0x0000ffff
#define HWSCH_STATUS_TAIL_HWSCH_STATUS_TAIL_DATA_GET(x)              (((x) & HWSCH_STATUS_TAIL_HWSCH_STATUS_TAIL_DATA_MASK) >> HWSCH_STATUS_TAIL_HWSCH_STATUS_TAIL_DATA_LSB)
#define HWSCH_STATUS_TAIL_HWSCH_STATUS_TAIL_DATA_SET(x)              (((0x0 | (x)) << HWSCH_STATUS_TAIL_HWSCH_STATUS_TAIL_DATA_LSB) & HWSCH_STATUS_TAIL_HWSCH_STATUS_TAIL_DATA_MASK)
#define HWSCH_STATUS_TAIL_HWSCH_STATUS_TAIL_DATA_RESET               0
#define HWSCH_STATUS_TAIL_ADDRESS                                    0x000268
#define HWSCH_STATUS_TAIL_HW_MASK                                    0xffffffff
#define HWSCH_STATUS_TAIL_SW_MASK                                    0xffffffff
#define HWSCH_STATUS_TAIL_RSTMASK                                    0x00000000
#define HWSCH_STATUS_TAIL_RESET                                      0x00000000

// 0x026c (HWSCH_RESP_TABLE_BASE)
#define HWSCH_RESP_TABLE_BASE_HWSCH_RESP_TABLE_BASE_DATA_MSB         31
#define HWSCH_RESP_TABLE_BASE_HWSCH_RESP_TABLE_BASE_DATA_LSB         0
#define HWSCH_RESP_TABLE_BASE_HWSCH_RESP_TABLE_BASE_DATA_MASK        0xffffffff
#define HWSCH_RESP_TABLE_BASE_HWSCH_RESP_TABLE_BASE_DATA_GET(x)      (((x) & HWSCH_RESP_TABLE_BASE_HWSCH_RESP_TABLE_BASE_DATA_MASK) >> HWSCH_RESP_TABLE_BASE_HWSCH_RESP_TABLE_BASE_DATA_LSB)
#define HWSCH_RESP_TABLE_BASE_HWSCH_RESP_TABLE_BASE_DATA_SET(x)      (((0x0 | (x)) << HWSCH_RESP_TABLE_BASE_HWSCH_RESP_TABLE_BASE_DATA_LSB) & HWSCH_RESP_TABLE_BASE_HWSCH_RESP_TABLE_BASE_DATA_MASK)
#define HWSCH_RESP_TABLE_BASE_HWSCH_RESP_TABLE_BASE_DATA_RESET       0
#define HWSCH_RESP_TABLE_BASE_ADDRESS                                0x00026c
#define HWSCH_RESP_TABLE_BASE_HW_MASK                                0xffffffff
#define HWSCH_RESP_TABLE_BASE_SW_MASK                                0xffffffff
#define HWSCH_RESP_TABLE_BASE_RSTMASK                                0x00000000
#define HWSCH_RESP_TABLE_BASE_RESET                                  0x00000000

// 0x0270 (HWSCH_RESP_TABLE_NUM_ENTRY)
#define HWSCH_RESP_TABLE_NUM_ENTRY_RESERVED_0_MSB                    31
#define HWSCH_RESP_TABLE_NUM_ENTRY_RESERVED_0_LSB                    16
#define HWSCH_RESP_TABLE_NUM_ENTRY_RESERVED_0_MASK                   0xffff0000
#define HWSCH_RESP_TABLE_NUM_ENTRY_RESERVED_0_GET(x)                 (((x) & HWSCH_RESP_TABLE_NUM_ENTRY_RESERVED_0_MASK) >> HWSCH_RESP_TABLE_NUM_ENTRY_RESERVED_0_LSB)
#define HWSCH_RESP_TABLE_NUM_ENTRY_RESERVED_0_SET(x)                 (((0x0 | (x)) << HWSCH_RESP_TABLE_NUM_ENTRY_RESERVED_0_LSB) & HWSCH_RESP_TABLE_NUM_ENTRY_RESERVED_0_MASK)
#define HWSCH_RESP_TABLE_NUM_ENTRY_RESERVED_0_RESET                  0
#define HWSCH_RESP_TABLE_NUM_ENTRY_HWSCH_RESP_TABLE_NUM_ENTRY_DATA_MSB 15
#define HWSCH_RESP_TABLE_NUM_ENTRY_HWSCH_RESP_TABLE_NUM_ENTRY_DATA_LSB 0
#define HWSCH_RESP_TABLE_NUM_ENTRY_HWSCH_RESP_TABLE_NUM_ENTRY_DATA_MASK 0x0000ffff
#define HWSCH_RESP_TABLE_NUM_ENTRY_HWSCH_RESP_TABLE_NUM_ENTRY_DATA_GET(x) (((x) & HWSCH_RESP_TABLE_NUM_ENTRY_HWSCH_RESP_TABLE_NUM_ENTRY_DATA_MASK) >> HWSCH_RESP_TABLE_NUM_ENTRY_HWSCH_RESP_TABLE_NUM_ENTRY_DATA_LSB)
#define HWSCH_RESP_TABLE_NUM_ENTRY_HWSCH_RESP_TABLE_NUM_ENTRY_DATA_SET(x) (((0x0 | (x)) << HWSCH_RESP_TABLE_NUM_ENTRY_HWSCH_RESP_TABLE_NUM_ENTRY_DATA_LSB) & HWSCH_RESP_TABLE_NUM_ENTRY_HWSCH_RESP_TABLE_NUM_ENTRY_DATA_MASK)
#define HWSCH_RESP_TABLE_NUM_ENTRY_HWSCH_RESP_TABLE_NUM_ENTRY_DATA_RESET 15
#define HWSCH_RESP_TABLE_NUM_ENTRY_ADDRESS                           0x000270
#define HWSCH_RESP_TABLE_NUM_ENTRY_HW_MASK                           0xffffffff
#define HWSCH_RESP_TABLE_NUM_ENTRY_SW_MASK                           0xffffffff
#define HWSCH_RESP_TABLE_NUM_ENTRY_RSTMASK                           0x0000ffff
#define HWSCH_RESP_TABLE_NUM_ENTRY_RESET                             0x0000000f

// 0x0274 (HWSCH_WATCHDOG_TIMER)
#define HWSCH_WATCHDOG_TIMER_RESERVED_0_MSB                          31
#define HWSCH_WATCHDOG_TIMER_RESERVED_0_LSB                          15
#define HWSCH_WATCHDOG_TIMER_RESERVED_0_MASK                         0xffff8000
#define HWSCH_WATCHDOG_TIMER_RESERVED_0_GET(x)                       (((x) & HWSCH_WATCHDOG_TIMER_RESERVED_0_MASK) >> HWSCH_WATCHDOG_TIMER_RESERVED_0_LSB)
#define HWSCH_WATCHDOG_TIMER_RESERVED_0_SET(x)                       (((0x0 | (x)) << HWSCH_WATCHDOG_TIMER_RESERVED_0_LSB) & HWSCH_WATCHDOG_TIMER_RESERVED_0_MASK)
#define HWSCH_WATCHDOG_TIMER_RESERVED_0_RESET                        0
#define HWSCH_WATCHDOG_TIMER_HWSCH_WATCHDOG_TIMEOUT_MSB              14
#define HWSCH_WATCHDOG_TIMER_HWSCH_WATCHDOG_TIMEOUT_LSB              0
#define HWSCH_WATCHDOG_TIMER_HWSCH_WATCHDOG_TIMEOUT_MASK             0x00007fff
#define HWSCH_WATCHDOG_TIMER_HWSCH_WATCHDOG_TIMEOUT_GET(x)           (((x) & HWSCH_WATCHDOG_TIMER_HWSCH_WATCHDOG_TIMEOUT_MASK) >> HWSCH_WATCHDOG_TIMER_HWSCH_WATCHDOG_TIMEOUT_LSB)
#define HWSCH_WATCHDOG_TIMER_HWSCH_WATCHDOG_TIMEOUT_SET(x)           (((0x0 | (x)) << HWSCH_WATCHDOG_TIMER_HWSCH_WATCHDOG_TIMEOUT_LSB) & HWSCH_WATCHDOG_TIMER_HWSCH_WATCHDOG_TIMEOUT_MASK)
#define HWSCH_WATCHDOG_TIMER_HWSCH_WATCHDOG_TIMEOUT_RESET            256
#define HWSCH_WATCHDOG_TIMER_ADDRESS                                 0x000274
#define HWSCH_WATCHDOG_TIMER_HW_MASK                                 0xffffffff
#define HWSCH_WATCHDOG_TIMER_SW_MASK                                 0xffffffff
#define HWSCH_WATCHDOG_TIMER_RSTMASK                                 0x00007fff
#define HWSCH_WATCHDOG_TIMER_RESET                                   0x00000100

// 0x0278 (HWSCH_PRE_BKOFF_TIMING_CTRL)
#define HWSCH_PRE_BKOFF_TIMING_CTRL_RESERVED_0_MSB                   31
#define HWSCH_PRE_BKOFF_TIMING_CTRL_RESERVED_0_LSB                   24
#define HWSCH_PRE_BKOFF_TIMING_CTRL_RESERVED_0_MASK                  0xff000000
#define HWSCH_PRE_BKOFF_TIMING_CTRL_RESERVED_0_GET(x)                (((x) & HWSCH_PRE_BKOFF_TIMING_CTRL_RESERVED_0_MASK) >> HWSCH_PRE_BKOFF_TIMING_CTRL_RESERVED_0_LSB)
#define HWSCH_PRE_BKOFF_TIMING_CTRL_RESERVED_0_SET(x)                (((0x0 | (x)) << HWSCH_PRE_BKOFF_TIMING_CTRL_RESERVED_0_LSB) & HWSCH_PRE_BKOFF_TIMING_CTRL_RESERVED_0_MASK)
#define HWSCH_PRE_BKOFF_TIMING_CTRL_RESERVED_0_RESET                 0
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_SLOTS_DATA_MSB   23
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_SLOTS_DATA_LSB   16
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_SLOTS_DATA_MASK  0x00ff0000
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_SLOTS_DATA_GET(x) (((x) & HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_SLOTS_DATA_MASK) >> HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_SLOTS_DATA_LSB)
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_SLOTS_DATA_SET(x) (((0x0 | (x)) << HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_SLOTS_DATA_LSB) & HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_SLOTS_DATA_MASK)
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_SLOTS_DATA_RESET 4
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_CLKS_DATA_MSB    15
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_CLKS_DATA_LSB    0
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_CLKS_DATA_MASK   0x0000ffff
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_CLKS_DATA_GET(x) (((x) & HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_CLKS_DATA_MASK) >> HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_CLKS_DATA_LSB)
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_CLKS_DATA_SET(x) (((0x0 | (x)) << HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_CLKS_DATA_LSB) & HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_CLKS_DATA_MASK)
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HWSCH_PRE_BKOFF_CLKS_DATA_RESET  0
#define HWSCH_PRE_BKOFF_TIMING_CTRL_ADDRESS                          0x000278
#define HWSCH_PRE_BKOFF_TIMING_CTRL_HW_MASK                          0xffffffff
#define HWSCH_PRE_BKOFF_TIMING_CTRL_SW_MASK                          0xffffffff
#define HWSCH_PRE_BKOFF_TIMING_CTRL_RSTMASK                          0x00ff0000
#define HWSCH_PRE_BKOFF_TIMING_CTRL_RESET                            0x00040000

// 0x027c (HWSCH_CMD_RING_PAUSE_CTRL)
#define HWSCH_CMD_RING_PAUSE_CTRL_RESERVED_0_MSB                     31
#define HWSCH_CMD_RING_PAUSE_CTRL_RESERVED_0_LSB                     16
#define HWSCH_CMD_RING_PAUSE_CTRL_RESERVED_0_MASK                    0xffff0000
#define HWSCH_CMD_RING_PAUSE_CTRL_RESERVED_0_GET(x)                  (((x) & HWSCH_CMD_RING_PAUSE_CTRL_RESERVED_0_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_RESERVED_0_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_RESERVED_0_SET(x)                  (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_RESERVED_0_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_RESERVED_0_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_RESERVED_0_RESET                   0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING15_PAUSED_MSB              15
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING15_PAUSED_LSB              15
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING15_PAUSED_MASK             0x00008000
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING15_PAUSED_GET(x)           (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING15_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING15_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING15_PAUSED_SET(x)           (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING15_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING15_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING15_PAUSED_RESET            0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING14_PAUSED_MSB              14
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING14_PAUSED_LSB              14
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING14_PAUSED_MASK             0x00004000
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING14_PAUSED_GET(x)           (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING14_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING14_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING14_PAUSED_SET(x)           (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING14_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING14_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING14_PAUSED_RESET            0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING13_PAUSED_MSB              13
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING13_PAUSED_LSB              13
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING13_PAUSED_MASK             0x00002000
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING13_PAUSED_GET(x)           (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING13_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING13_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING13_PAUSED_SET(x)           (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING13_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING13_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING13_PAUSED_RESET            0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING12_PAUSED_MSB              12
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING12_PAUSED_LSB              12
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING12_PAUSED_MASK             0x00001000
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING12_PAUSED_GET(x)           (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING12_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING12_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING12_PAUSED_SET(x)           (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING12_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING12_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING12_PAUSED_RESET            0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING11_PAUSED_MSB              11
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING11_PAUSED_LSB              11
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING11_PAUSED_MASK             0x00000800
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING11_PAUSED_GET(x)           (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING11_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING11_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING11_PAUSED_SET(x)           (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING11_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING11_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING11_PAUSED_RESET            0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING10_PAUSED_MSB              10
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING10_PAUSED_LSB              10
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING10_PAUSED_MASK             0x00000400
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING10_PAUSED_GET(x)           (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING10_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING10_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING10_PAUSED_SET(x)           (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING10_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING10_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING10_PAUSED_RESET            0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING9_PAUSED_MSB               9
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING9_PAUSED_LSB               9
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING9_PAUSED_MASK              0x00000200
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING9_PAUSED_GET(x)            (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING9_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING9_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING9_PAUSED_SET(x)            (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING9_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING9_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING9_PAUSED_RESET             0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING8_PAUSED_MSB               8
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING8_PAUSED_LSB               8
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING8_PAUSED_MASK              0x00000100
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING8_PAUSED_GET(x)            (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING8_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING8_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING8_PAUSED_SET(x)            (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING8_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING8_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING8_PAUSED_RESET             0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING7_PAUSED_MSB               7
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING7_PAUSED_LSB               7
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING7_PAUSED_MASK              0x00000080
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING7_PAUSED_GET(x)            (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING7_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING7_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING7_PAUSED_SET(x)            (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING7_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING7_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING7_PAUSED_RESET             0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING6_PAUSED_MSB               6
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING6_PAUSED_LSB               6
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING6_PAUSED_MASK              0x00000040
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING6_PAUSED_GET(x)            (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING6_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING6_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING6_PAUSED_SET(x)            (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING6_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING6_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING6_PAUSED_RESET             0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING5_PAUSED_MSB               5
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING5_PAUSED_LSB               5
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING5_PAUSED_MASK              0x00000020
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING5_PAUSED_GET(x)            (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING5_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING5_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING5_PAUSED_SET(x)            (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING5_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING5_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING5_PAUSED_RESET             0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING4_PAUSED_MSB               4
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING4_PAUSED_LSB               4
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING4_PAUSED_MASK              0x00000010
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING4_PAUSED_GET(x)            (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING4_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING4_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING4_PAUSED_SET(x)            (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING4_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING4_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING4_PAUSED_RESET             0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING3_PAUSED_MSB               3
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING3_PAUSED_LSB               3
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING3_PAUSED_MASK              0x00000008
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING3_PAUSED_GET(x)            (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING3_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING3_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING3_PAUSED_SET(x)            (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING3_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING3_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING3_PAUSED_RESET             0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING2_PAUSED_MSB               2
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING2_PAUSED_LSB               2
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING2_PAUSED_MASK              0x00000004
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING2_PAUSED_GET(x)            (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING2_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING2_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING2_PAUSED_SET(x)            (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING2_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING2_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING2_PAUSED_RESET             0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING1_PAUSED_MSB               1
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING1_PAUSED_LSB               1
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING1_PAUSED_MASK              0x00000002
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING1_PAUSED_GET(x)            (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING1_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING1_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING1_PAUSED_SET(x)            (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING1_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING1_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING1_PAUSED_RESET             0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING0_PAUSED_MSB               0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING0_PAUSED_LSB               0
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING0_PAUSED_MASK              0x00000001
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING0_PAUSED_GET(x)            (((x) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING0_PAUSED_MASK) >> HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING0_PAUSED_LSB)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING0_PAUSED_SET(x)            (((0x0 | (x)) << HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING0_PAUSED_LSB) & HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING0_PAUSED_MASK)
#define HWSCH_CMD_RING_PAUSE_CTRL_CMD_RING0_PAUSED_RESET             0
#define HWSCH_CMD_RING_PAUSE_CTRL_ADDRESS                            0x00027c
#define HWSCH_CMD_RING_PAUSE_CTRL_HW_MASK                            0xffffffff
#define HWSCH_CMD_RING_PAUSE_CTRL_SW_MASK                            0xffffffff
#define HWSCH_CMD_RING_PAUSE_CTRL_RSTMASK                            0x00000000
#define HWSCH_CMD_RING_PAUSE_CTRL_RESET                              0x00000000

// 0x0280 (HWSCH_MODE_CTRL)
#define HWSCH_MODE_CTRL_RESERVED_0_MSB                               31
#define HWSCH_MODE_CTRL_RESERVED_0_LSB                               16
#define HWSCH_MODE_CTRL_RESERVED_0_MASK                              0xffff0000
#define HWSCH_MODE_CTRL_RESERVED_0_GET(x)                            (((x) & HWSCH_MODE_CTRL_RESERVED_0_MASK) >> HWSCH_MODE_CTRL_RESERVED_0_LSB)
#define HWSCH_MODE_CTRL_RESERVED_0_SET(x)                            (((0x0 | (x)) << HWSCH_MODE_CTRL_RESERVED_0_LSB) & HWSCH_MODE_CTRL_RESERVED_0_MASK)
#define HWSCH_MODE_CTRL_RESERVED_0_RESET                             0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING15_MSB             15
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING15_LSB             15
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING15_MASK            0x00008000
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING15_GET(x)          (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING15_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING15_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING15_SET(x)          (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING15_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING15_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING15_RESET           0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING14_MSB             14
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING14_LSB             14
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING14_MASK            0x00004000
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING14_GET(x)          (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING14_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING14_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING14_SET(x)          (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING14_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING14_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING14_RESET           0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING13_MSB             13
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING13_LSB             13
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING13_MASK            0x00002000
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING13_GET(x)          (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING13_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING13_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING13_SET(x)          (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING13_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING13_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING13_RESET           0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING12_MSB             12
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING12_LSB             12
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING12_MASK            0x00001000
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING12_GET(x)          (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING12_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING12_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING12_SET(x)          (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING12_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING12_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING12_RESET           0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING11_MSB             11
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING11_LSB             11
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING11_MASK            0x00000800
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING11_GET(x)          (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING11_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING11_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING11_SET(x)          (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING11_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING11_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING11_RESET           0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING10_MSB             10
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING10_LSB             10
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING10_MASK            0x00000400
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING10_GET(x)          (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING10_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING10_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING10_SET(x)          (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING10_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING10_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING10_RESET           0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING9_MSB              9
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING9_LSB              9
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING9_MASK             0x00000200
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING9_GET(x)           (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING9_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING9_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING9_SET(x)           (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING9_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING9_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING9_RESET            0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING8_MSB              8
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING8_LSB              8
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING8_MASK             0x00000100
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING8_GET(x)           (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING8_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING8_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING8_SET(x)           (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING8_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING8_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING8_RESET            0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING7_MSB              7
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING7_LSB              7
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING7_MASK             0x00000080
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING7_GET(x)           (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING7_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING7_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING7_SET(x)           (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING7_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING7_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING7_RESET            0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING6_MSB              6
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING6_LSB              6
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING6_MASK             0x00000040
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING6_GET(x)           (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING6_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING6_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING6_SET(x)           (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING6_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING6_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING6_RESET            0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING5_MSB              5
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING5_LSB              5
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING5_MASK             0x00000020
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING5_GET(x)           (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING5_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING5_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING5_SET(x)           (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING5_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING5_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING5_RESET            0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING4_MSB              4
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING4_LSB              4
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING4_MASK             0x00000010
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING4_GET(x)           (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING4_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING4_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING4_SET(x)           (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING4_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING4_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING4_RESET            0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING3_MSB              3
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING3_LSB              3
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING3_MASK             0x00000008
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING3_GET(x)           (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING3_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING3_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING3_SET(x)           (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING3_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING3_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING3_RESET            0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING2_MSB              2
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING2_LSB              2
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING2_MASK             0x00000004
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING2_GET(x)           (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING2_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING2_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING2_SET(x)           (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING2_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING2_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING2_RESET            0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING1_MSB              1
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING1_LSB              1
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING1_MASK             0x00000002
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING1_GET(x)           (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING1_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING1_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING1_SET(x)           (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING1_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING1_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING1_RESET            0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING0_MSB              0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING0_LSB              0
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING0_MASK             0x00000001
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING0_GET(x)           (((x) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING0_MASK) >> HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING0_LSB)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING0_SET(x)           (((0x0 | (x)) << HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING0_LSB) & HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING0_MASK)
#define HWSCH_MODE_CTRL_HWSCH_CONTINUOUS_MODE_RING0_RESET            0
#define HWSCH_MODE_CTRL_ADDRESS                                      0x000280
#define HWSCH_MODE_CTRL_HW_MASK                                      0xffffffff
#define HWSCH_MODE_CTRL_SW_MASK                                      0xffffffff
#define HWSCH_MODE_CTRL_RSTMASK                                      0x00000000
#define HWSCH_MODE_CTRL_RESET                                        0x00000000

// 0x0284 (HWSCH_PAUSE_REASON_SCH_CMD_0)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_SCH_CMD_ILLEGAL_STATE_MSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_0_SCH_CMD_ILLEGAL_STATE_LSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_0_SCH_CMD_ILLEGAL_STATE_MASK      0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_0_SCH_CMD_ILLEGAL_STATE_GET(x)    (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_SCH_CMD_ILLEGAL_STATE_SET(x)    (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_SCH_CMD_ILLEGAL_STATE_RESET     0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_RESERVED_0_MSB                  30
#define HWSCH_PAUSE_REASON_SCH_CMD_0_RESERVED_0_LSB                  13
#define HWSCH_PAUSE_REASON_SCH_CMD_0_RESERVED_0_MASK                 0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_0_RESERVED_0_GET(x)               (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_RESERVED_0_RESET                0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_FES_SETUP_ABORT_MSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_0_FES_SETUP_ABORT_LSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_0_FES_SETUP_ABORT_MASK            0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_0_FES_SETUP_ABORT_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_FES_SETUP_ABORT_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_FES_SETUP_ABORT_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR2_MSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR2_LSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR2_MASK            0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR2_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR2_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR2_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR2_MSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR2_LSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR2_MASK          0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR2_MSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR2_LSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR2_MASK           0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR2_MSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR2_LSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR1_MSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR1_LSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR1_MASK            0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR1_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR1_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR1_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR1_MSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR1_LSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR1_MASK          0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR1_MSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR1_LSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR1_MASK           0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR1_MSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR1_LSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR0_MSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR0_LSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR0_MASK            0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR0_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR0_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_NULL_QUEUE_USR0_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR0_MSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR0_LSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR0_MASK          0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QUEUE_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR0_MSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR0_LSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR0_MASK           0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_QMGR_PAUSED_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR0_MSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR0_LSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_0_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_0_ADDRESS                         0x000284
#define HWSCH_PAUSE_REASON_SCH_CMD_0_HW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_0_SW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_0_RSTMASK                         0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_0_RESET                           0x00000000

// 0x0288 (HWSCH_PAUSE_REASON_SCH_CMD_1)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_SCH_CMD_ILLEGAL_STATE_MSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_1_SCH_CMD_ILLEGAL_STATE_LSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_1_SCH_CMD_ILLEGAL_STATE_MASK      0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_1_SCH_CMD_ILLEGAL_STATE_GET(x)    (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_SCH_CMD_ILLEGAL_STATE_SET(x)    (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_SCH_CMD_ILLEGAL_STATE_RESET     0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_RESERVED_0_MSB                  30
#define HWSCH_PAUSE_REASON_SCH_CMD_1_RESERVED_0_LSB                  13
#define HWSCH_PAUSE_REASON_SCH_CMD_1_RESERVED_0_MASK                 0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_1_RESERVED_0_GET(x)               (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_RESERVED_0_RESET                0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_FES_SETUP_ABORT_MSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_1_FES_SETUP_ABORT_LSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_1_FES_SETUP_ABORT_MASK            0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_1_FES_SETUP_ABORT_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_FES_SETUP_ABORT_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_FES_SETUP_ABORT_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR2_MSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR2_LSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR2_MASK            0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR2_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR2_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR2_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR2_MSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR2_LSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR2_MASK          0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR2_MSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR2_LSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR2_MASK           0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR2_MSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR2_LSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR1_MSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR1_LSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR1_MASK            0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR1_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR1_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR1_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR1_MSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR1_LSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR1_MASK          0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR1_MSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR1_LSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR1_MASK           0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR1_MSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR1_LSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR0_MSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR0_LSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR0_MASK            0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR0_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR0_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_NULL_QUEUE_USR0_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR0_MSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR0_LSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR0_MASK          0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QUEUE_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR0_MSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR0_LSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR0_MASK           0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_QMGR_PAUSED_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR0_MSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR0_LSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_1_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_1_ADDRESS                         0x000288
#define HWSCH_PAUSE_REASON_SCH_CMD_1_HW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_1_SW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_1_RSTMASK                         0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_1_RESET                           0x00000000

// 0x028c (HWSCH_PAUSE_REASON_SCH_CMD_2)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_SCH_CMD_ILLEGAL_STATE_MSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_2_SCH_CMD_ILLEGAL_STATE_LSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_2_SCH_CMD_ILLEGAL_STATE_MASK      0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_2_SCH_CMD_ILLEGAL_STATE_GET(x)    (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_SCH_CMD_ILLEGAL_STATE_SET(x)    (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_SCH_CMD_ILLEGAL_STATE_RESET     0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_RESERVED_0_MSB                  30
#define HWSCH_PAUSE_REASON_SCH_CMD_2_RESERVED_0_LSB                  13
#define HWSCH_PAUSE_REASON_SCH_CMD_2_RESERVED_0_MASK                 0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_2_RESERVED_0_GET(x)               (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_RESERVED_0_RESET                0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_FES_SETUP_ABORT_MSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_2_FES_SETUP_ABORT_LSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_2_FES_SETUP_ABORT_MASK            0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_2_FES_SETUP_ABORT_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_FES_SETUP_ABORT_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_FES_SETUP_ABORT_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR2_MSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR2_LSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR2_MASK            0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR2_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR2_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR2_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR2_MSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR2_LSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR2_MASK          0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR2_MSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR2_LSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR2_MASK           0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR2_MSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR2_LSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR1_MSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR1_LSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR1_MASK            0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR1_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR1_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR1_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR1_MSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR1_LSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR1_MASK          0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR1_MSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR1_LSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR1_MASK           0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR1_MSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR1_LSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR0_MSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR0_LSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR0_MASK            0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR0_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR0_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_NULL_QUEUE_USR0_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR0_MSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR0_LSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR0_MASK          0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QUEUE_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR0_MSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR0_LSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR0_MASK           0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_QMGR_PAUSED_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR0_MSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR0_LSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_2_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_2_ADDRESS                         0x00028c
#define HWSCH_PAUSE_REASON_SCH_CMD_2_HW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_2_SW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_2_RSTMASK                         0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_2_RESET                           0x00000000

// 0x0290 (HWSCH_PAUSE_REASON_SCH_CMD_3)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_SCH_CMD_ILLEGAL_STATE_MSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_3_SCH_CMD_ILLEGAL_STATE_LSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_3_SCH_CMD_ILLEGAL_STATE_MASK      0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_3_SCH_CMD_ILLEGAL_STATE_GET(x)    (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_SCH_CMD_ILLEGAL_STATE_SET(x)    (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_SCH_CMD_ILLEGAL_STATE_RESET     0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_RESERVED_0_MSB                  30
#define HWSCH_PAUSE_REASON_SCH_CMD_3_RESERVED_0_LSB                  13
#define HWSCH_PAUSE_REASON_SCH_CMD_3_RESERVED_0_MASK                 0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_3_RESERVED_0_GET(x)               (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_RESERVED_0_RESET                0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_FES_SETUP_ABORT_MSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_3_FES_SETUP_ABORT_LSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_3_FES_SETUP_ABORT_MASK            0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_3_FES_SETUP_ABORT_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_FES_SETUP_ABORT_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_FES_SETUP_ABORT_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR2_MSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR2_LSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR2_MASK            0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR2_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR2_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR2_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR2_MSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR2_LSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR2_MASK          0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR2_MSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR2_LSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR2_MASK           0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR2_MSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR2_LSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR1_MSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR1_LSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR1_MASK            0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR1_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR1_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR1_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR1_MSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR1_LSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR1_MASK          0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR1_MSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR1_LSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR1_MASK           0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR1_MSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR1_LSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR0_MSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR0_LSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR0_MASK            0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR0_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR0_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_NULL_QUEUE_USR0_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR0_MSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR0_LSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR0_MASK          0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QUEUE_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR0_MSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR0_LSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR0_MASK           0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_QMGR_PAUSED_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR0_MSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR0_LSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_3_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_3_ADDRESS                         0x000290
#define HWSCH_PAUSE_REASON_SCH_CMD_3_HW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_3_SW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_3_RSTMASK                         0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_3_RESET                           0x00000000

// 0x0294 (HWSCH_PAUSE_REASON_SCH_CMD_4)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_SCH_CMD_ILLEGAL_STATE_MSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_4_SCH_CMD_ILLEGAL_STATE_LSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_4_SCH_CMD_ILLEGAL_STATE_MASK      0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_4_SCH_CMD_ILLEGAL_STATE_GET(x)    (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_SCH_CMD_ILLEGAL_STATE_SET(x)    (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_SCH_CMD_ILLEGAL_STATE_RESET     0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_RESERVED_0_MSB                  30
#define HWSCH_PAUSE_REASON_SCH_CMD_4_RESERVED_0_LSB                  13
#define HWSCH_PAUSE_REASON_SCH_CMD_4_RESERVED_0_MASK                 0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_4_RESERVED_0_GET(x)               (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_RESERVED_0_RESET                0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_FES_SETUP_ABORT_MSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_4_FES_SETUP_ABORT_LSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_4_FES_SETUP_ABORT_MASK            0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_4_FES_SETUP_ABORT_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_FES_SETUP_ABORT_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_FES_SETUP_ABORT_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR2_MSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR2_LSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR2_MASK            0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR2_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR2_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR2_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR2_MSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR2_LSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR2_MASK          0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR2_MSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR2_LSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR2_MASK           0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR2_MSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR2_LSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR1_MSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR1_LSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR1_MASK            0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR1_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR1_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR1_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR1_MSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR1_LSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR1_MASK          0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR1_MSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR1_LSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR1_MASK           0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR1_MSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR1_LSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR0_MSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR0_LSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR0_MASK            0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR0_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR0_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_NULL_QUEUE_USR0_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR0_MSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR0_LSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR0_MASK          0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QUEUE_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR0_MSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR0_LSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR0_MASK           0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_QMGR_PAUSED_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR0_MSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR0_LSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_4_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_4_ADDRESS                         0x000294
#define HWSCH_PAUSE_REASON_SCH_CMD_4_HW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_4_SW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_4_RSTMASK                         0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_4_RESET                           0x00000000

// 0x0298 (HWSCH_PAUSE_REASON_SCH_CMD_5)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_SCH_CMD_ILLEGAL_STATE_MSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_5_SCH_CMD_ILLEGAL_STATE_LSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_5_SCH_CMD_ILLEGAL_STATE_MASK      0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_5_SCH_CMD_ILLEGAL_STATE_GET(x)    (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_SCH_CMD_ILLEGAL_STATE_SET(x)    (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_SCH_CMD_ILLEGAL_STATE_RESET     0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_RESERVED_0_MSB                  30
#define HWSCH_PAUSE_REASON_SCH_CMD_5_RESERVED_0_LSB                  13
#define HWSCH_PAUSE_REASON_SCH_CMD_5_RESERVED_0_MASK                 0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_5_RESERVED_0_GET(x)               (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_RESERVED_0_RESET                0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_FES_SETUP_ABORT_MSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_5_FES_SETUP_ABORT_LSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_5_FES_SETUP_ABORT_MASK            0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_5_FES_SETUP_ABORT_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_FES_SETUP_ABORT_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_FES_SETUP_ABORT_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR2_MSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR2_LSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR2_MASK            0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR2_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR2_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR2_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR2_MSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR2_LSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR2_MASK          0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR2_MSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR2_LSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR2_MASK           0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR2_MSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR2_LSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR1_MSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR1_LSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR1_MASK            0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR1_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR1_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR1_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR1_MSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR1_LSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR1_MASK          0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR1_MSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR1_LSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR1_MASK           0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR1_MSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR1_LSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR0_MSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR0_LSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR0_MASK            0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR0_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR0_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_NULL_QUEUE_USR0_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR0_MSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR0_LSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR0_MASK          0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QUEUE_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR0_MSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR0_LSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR0_MASK           0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_QMGR_PAUSED_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR0_MSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR0_LSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_5_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_5_ADDRESS                         0x000298
#define HWSCH_PAUSE_REASON_SCH_CMD_5_HW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_5_SW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_5_RSTMASK                         0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_5_RESET                           0x00000000

// 0x029c (HWSCH_PAUSE_REASON_SCH_CMD_6)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_SCH_CMD_ILLEGAL_STATE_MSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_6_SCH_CMD_ILLEGAL_STATE_LSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_6_SCH_CMD_ILLEGAL_STATE_MASK      0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_6_SCH_CMD_ILLEGAL_STATE_GET(x)    (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_SCH_CMD_ILLEGAL_STATE_SET(x)    (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_SCH_CMD_ILLEGAL_STATE_RESET     0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_RESERVED_0_MSB                  30
#define HWSCH_PAUSE_REASON_SCH_CMD_6_RESERVED_0_LSB                  13
#define HWSCH_PAUSE_REASON_SCH_CMD_6_RESERVED_0_MASK                 0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_6_RESERVED_0_GET(x)               (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_RESERVED_0_RESET                0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_FES_SETUP_ABORT_MSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_6_FES_SETUP_ABORT_LSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_6_FES_SETUP_ABORT_MASK            0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_6_FES_SETUP_ABORT_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_FES_SETUP_ABORT_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_FES_SETUP_ABORT_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR2_MSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR2_LSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR2_MASK            0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR2_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR2_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR2_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR2_MSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR2_LSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR2_MASK          0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR2_MSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR2_LSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR2_MASK           0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR2_MSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR2_LSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR1_MSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR1_LSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR1_MASK            0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR1_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR1_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR1_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR1_MSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR1_LSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR1_MASK          0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR1_MSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR1_LSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR1_MASK           0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR1_MSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR1_LSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR0_MSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR0_LSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR0_MASK            0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR0_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR0_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_NULL_QUEUE_USR0_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR0_MSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR0_LSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR0_MASK          0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QUEUE_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR0_MSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR0_LSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR0_MASK           0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_QMGR_PAUSED_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR0_MSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR0_LSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_6_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_6_ADDRESS                         0x00029c
#define HWSCH_PAUSE_REASON_SCH_CMD_6_HW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_6_SW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_6_RSTMASK                         0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_6_RESET                           0x00000000

// 0x02a0 (HWSCH_PAUSE_REASON_SCH_CMD_7)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_SCH_CMD_ILLEGAL_STATE_MSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_7_SCH_CMD_ILLEGAL_STATE_LSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_7_SCH_CMD_ILLEGAL_STATE_MASK      0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_7_SCH_CMD_ILLEGAL_STATE_GET(x)    (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_SCH_CMD_ILLEGAL_STATE_SET(x)    (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_SCH_CMD_ILLEGAL_STATE_RESET     0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_RESERVED_0_MSB                  30
#define HWSCH_PAUSE_REASON_SCH_CMD_7_RESERVED_0_LSB                  13
#define HWSCH_PAUSE_REASON_SCH_CMD_7_RESERVED_0_MASK                 0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_7_RESERVED_0_GET(x)               (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_RESERVED_0_RESET                0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_FES_SETUP_ABORT_MSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_7_FES_SETUP_ABORT_LSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_7_FES_SETUP_ABORT_MASK            0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_7_FES_SETUP_ABORT_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_FES_SETUP_ABORT_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_FES_SETUP_ABORT_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR2_MSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR2_LSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR2_MASK            0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR2_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR2_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR2_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR2_MSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR2_LSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR2_MASK          0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR2_MSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR2_LSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR2_MASK           0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR2_MSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR2_LSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR1_MSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR1_LSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR1_MASK            0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR1_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR1_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR1_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR1_MSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR1_LSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR1_MASK          0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR1_MSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR1_LSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR1_MASK           0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR1_MSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR1_LSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR0_MSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR0_LSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR0_MASK            0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR0_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR0_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_NULL_QUEUE_USR0_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR0_MSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR0_LSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR0_MASK          0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QUEUE_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR0_MSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR0_LSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR0_MASK           0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_QMGR_PAUSED_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR0_MSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR0_LSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_7_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_ADDRESS                         0x0002a0
#define HWSCH_PAUSE_REASON_SCH_CMD_7_HW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_7_SW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_7_RSTMASK                         0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_7_RESET                           0x00000000

// 0x02a4 (HWSCH_PAUSE_REASON_SCH_CMD_8)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_SCH_CMD_ILLEGAL_STATE_MSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_8_SCH_CMD_ILLEGAL_STATE_LSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_8_SCH_CMD_ILLEGAL_STATE_MASK      0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_8_SCH_CMD_ILLEGAL_STATE_GET(x)    (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_SCH_CMD_ILLEGAL_STATE_SET(x)    (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_SCH_CMD_ILLEGAL_STATE_RESET     0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_RESERVED_0_MSB                  30
#define HWSCH_PAUSE_REASON_SCH_CMD_8_RESERVED_0_LSB                  13
#define HWSCH_PAUSE_REASON_SCH_CMD_8_RESERVED_0_MASK                 0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_8_RESERVED_0_GET(x)               (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_RESERVED_0_RESET                0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_FES_SETUP_ABORT_MSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_8_FES_SETUP_ABORT_LSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_8_FES_SETUP_ABORT_MASK            0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_8_FES_SETUP_ABORT_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_FES_SETUP_ABORT_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_FES_SETUP_ABORT_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR2_MSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR2_LSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR2_MASK            0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR2_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR2_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR2_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR2_MSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR2_LSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR2_MASK          0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR2_MSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR2_LSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR2_MASK           0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR2_MSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR2_LSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR1_MSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR1_LSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR1_MASK            0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR1_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR1_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR1_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR1_MSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR1_LSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR1_MASK          0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR1_MSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR1_LSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR1_MASK           0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR1_MSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR1_LSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR0_MSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR0_LSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR0_MASK            0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR0_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR0_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_NULL_QUEUE_USR0_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR0_MSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR0_LSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR0_MASK          0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QUEUE_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR0_MSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR0_LSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR0_MASK           0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_QMGR_PAUSED_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR0_MSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR0_LSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_8_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_8_ADDRESS                         0x0002a4
#define HWSCH_PAUSE_REASON_SCH_CMD_8_HW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_8_SW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_8_RSTMASK                         0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_8_RESET                           0x00000000

// 0x02a8 (HWSCH_PAUSE_REASON_SCH_CMD_9)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_SCH_CMD_ILLEGAL_STATE_MSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_9_SCH_CMD_ILLEGAL_STATE_LSB       31
#define HWSCH_PAUSE_REASON_SCH_CMD_9_SCH_CMD_ILLEGAL_STATE_MASK      0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_9_SCH_CMD_ILLEGAL_STATE_GET(x)    (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_SCH_CMD_ILLEGAL_STATE_SET(x)    (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_SCH_CMD_ILLEGAL_STATE_RESET     0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_RESERVED_0_MSB                  30
#define HWSCH_PAUSE_REASON_SCH_CMD_9_RESERVED_0_LSB                  13
#define HWSCH_PAUSE_REASON_SCH_CMD_9_RESERVED_0_MASK                 0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_9_RESERVED_0_GET(x)               (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_RESERVED_0_SET(x)               (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_RESERVED_0_RESET                0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_FES_SETUP_ABORT_MSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_9_FES_SETUP_ABORT_LSB             12
#define HWSCH_PAUSE_REASON_SCH_CMD_9_FES_SETUP_ABORT_MASK            0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_9_FES_SETUP_ABORT_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_FES_SETUP_ABORT_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_FES_SETUP_ABORT_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR2_MSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR2_LSB             11
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR2_MASK            0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR2_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR2_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR2_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR2_MSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR2_LSB           10
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR2_MASK          0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR2_MSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR2_LSB            9
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR2_MASK           0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR2_MSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR2_LSB  8
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR1_MSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR1_LSB             7
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR1_MASK            0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR1_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR1_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR1_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR1_MSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR1_LSB           6
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR1_MASK          0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR1_MSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR1_LSB            5
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR1_MASK           0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR1_MSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR1_LSB  4
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR0_MSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR0_LSB             3
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR0_MASK            0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR0_GET(x)          (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR0_SET(x)          (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_NULL_QUEUE_USR0_RESET           0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR0_MSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR0_LSB           2
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR0_MASK          0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QUEUE_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR0_MSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR0_LSB            1
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR0_MASK           0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_QMGR_PAUSED_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR0_MSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR0_LSB  0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_9_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_9_ADDRESS                         0x0002a8
#define HWSCH_PAUSE_REASON_SCH_CMD_9_HW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_9_SW_MASK                         0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_9_RSTMASK                         0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_9_RESET                           0x00000000

// 0x02ac (HWSCH_PAUSE_REASON_SCH_CMD_10)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_SCH_CMD_ILLEGAL_STATE_MSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_10_SCH_CMD_ILLEGAL_STATE_LSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_10_SCH_CMD_ILLEGAL_STATE_MASK     0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_10_SCH_CMD_ILLEGAL_STATE_GET(x)   (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_SCH_CMD_ILLEGAL_STATE_SET(x)   (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_SCH_CMD_ILLEGAL_STATE_RESET    0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_RESERVED_0_MSB                 30
#define HWSCH_PAUSE_REASON_SCH_CMD_10_RESERVED_0_LSB                 13
#define HWSCH_PAUSE_REASON_SCH_CMD_10_RESERVED_0_MASK                0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_10_RESERVED_0_GET(x)              (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_RESERVED_0_SET(x)              (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_RESERVED_0_RESET               0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_FES_SETUP_ABORT_MSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_10_FES_SETUP_ABORT_LSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_10_FES_SETUP_ABORT_MASK           0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_10_FES_SETUP_ABORT_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_FES_SETUP_ABORT_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_FES_SETUP_ABORT_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR2_MSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR2_LSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR2_MASK           0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR2_MSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR2_LSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR2_MASK         0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR2_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR2_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR2_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR2_MSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR2_LSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR2_MASK          0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR2_MSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR2_LSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR1_MSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR1_LSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR1_MASK           0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR1_MSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR1_LSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR1_MASK         0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR1_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR1_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR1_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR1_MSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR1_LSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR1_MASK          0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR1_MSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR1_LSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR0_MSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR0_LSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR0_MASK           0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_NULL_QUEUE_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR0_MSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR0_LSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR0_MASK         0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR0_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR0_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QUEUE_PAUSED_USR0_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR0_MSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR0_LSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR0_MASK          0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_QMGR_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR0_MSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR0_LSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_10_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_10_ADDRESS                        0x0002ac
#define HWSCH_PAUSE_REASON_SCH_CMD_10_HW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_10_SW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_10_RSTMASK                        0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_10_RESET                          0x00000000

// 0x02b0 (HWSCH_PAUSE_REASON_SCH_CMD_11)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_SCH_CMD_ILLEGAL_STATE_MSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_11_SCH_CMD_ILLEGAL_STATE_LSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_11_SCH_CMD_ILLEGAL_STATE_MASK     0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_11_SCH_CMD_ILLEGAL_STATE_GET(x)   (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_SCH_CMD_ILLEGAL_STATE_SET(x)   (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_SCH_CMD_ILLEGAL_STATE_RESET    0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_RESERVED_0_MSB                 30
#define HWSCH_PAUSE_REASON_SCH_CMD_11_RESERVED_0_LSB                 13
#define HWSCH_PAUSE_REASON_SCH_CMD_11_RESERVED_0_MASK                0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_11_RESERVED_0_GET(x)              (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_RESERVED_0_SET(x)              (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_RESERVED_0_RESET               0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_FES_SETUP_ABORT_MSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_11_FES_SETUP_ABORT_LSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_11_FES_SETUP_ABORT_MASK           0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_11_FES_SETUP_ABORT_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_FES_SETUP_ABORT_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_FES_SETUP_ABORT_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR2_MSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR2_LSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR2_MASK           0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR2_MSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR2_LSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR2_MASK         0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR2_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR2_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR2_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR2_MSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR2_LSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR2_MASK          0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR2_MSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR2_LSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR1_MSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR1_LSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR1_MASK           0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR1_MSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR1_LSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR1_MASK         0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR1_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR1_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR1_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR1_MSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR1_LSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR1_MASK          0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR1_MSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR1_LSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR0_MSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR0_LSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR0_MASK           0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_NULL_QUEUE_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR0_MSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR0_LSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR0_MASK         0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR0_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR0_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QUEUE_PAUSED_USR0_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR0_MSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR0_LSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR0_MASK          0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_QMGR_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR0_MSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR0_LSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_11_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_ADDRESS                        0x0002b0
#define HWSCH_PAUSE_REASON_SCH_CMD_11_HW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_11_SW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_11_RSTMASK                        0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_11_RESET                          0x00000000

// 0x02b4 (HWSCH_PAUSE_REASON_SCH_CMD_12)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_SCH_CMD_ILLEGAL_STATE_MSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_12_SCH_CMD_ILLEGAL_STATE_LSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_12_SCH_CMD_ILLEGAL_STATE_MASK     0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_12_SCH_CMD_ILLEGAL_STATE_GET(x)   (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_SCH_CMD_ILLEGAL_STATE_SET(x)   (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_SCH_CMD_ILLEGAL_STATE_RESET    0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_RESERVED_0_MSB                 30
#define HWSCH_PAUSE_REASON_SCH_CMD_12_RESERVED_0_LSB                 13
#define HWSCH_PAUSE_REASON_SCH_CMD_12_RESERVED_0_MASK                0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_12_RESERVED_0_GET(x)              (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_RESERVED_0_SET(x)              (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_RESERVED_0_RESET               0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_FES_SETUP_ABORT_MSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_12_FES_SETUP_ABORT_LSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_12_FES_SETUP_ABORT_MASK           0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_12_FES_SETUP_ABORT_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_FES_SETUP_ABORT_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_FES_SETUP_ABORT_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR2_MSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR2_LSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR2_MASK           0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR2_MSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR2_LSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR2_MASK         0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR2_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR2_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR2_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR2_MSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR2_LSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR2_MASK          0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR2_MSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR2_LSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR1_MSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR1_LSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR1_MASK           0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR1_MSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR1_LSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR1_MASK         0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR1_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR1_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR1_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR1_MSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR1_LSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR1_MASK          0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR1_MSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR1_LSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR0_MSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR0_LSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR0_MASK           0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_NULL_QUEUE_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR0_MSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR0_LSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR0_MASK         0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR0_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR0_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QUEUE_PAUSED_USR0_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR0_MSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR0_LSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR0_MASK          0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_QMGR_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR0_MSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR0_LSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_12_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_12_ADDRESS                        0x0002b4
#define HWSCH_PAUSE_REASON_SCH_CMD_12_HW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_12_SW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_12_RSTMASK                        0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_12_RESET                          0x00000000

// 0x02b8 (HWSCH_PAUSE_REASON_SCH_CMD_13)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_SCH_CMD_ILLEGAL_STATE_MSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_13_SCH_CMD_ILLEGAL_STATE_LSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_13_SCH_CMD_ILLEGAL_STATE_MASK     0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_13_SCH_CMD_ILLEGAL_STATE_GET(x)   (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_SCH_CMD_ILLEGAL_STATE_SET(x)   (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_SCH_CMD_ILLEGAL_STATE_RESET    0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_RESERVED_0_MSB                 30
#define HWSCH_PAUSE_REASON_SCH_CMD_13_RESERVED_0_LSB                 13
#define HWSCH_PAUSE_REASON_SCH_CMD_13_RESERVED_0_MASK                0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_13_RESERVED_0_GET(x)              (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_RESERVED_0_SET(x)              (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_RESERVED_0_RESET               0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_FES_SETUP_ABORT_MSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_13_FES_SETUP_ABORT_LSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_13_FES_SETUP_ABORT_MASK           0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_13_FES_SETUP_ABORT_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_FES_SETUP_ABORT_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_FES_SETUP_ABORT_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR2_MSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR2_LSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR2_MASK           0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR2_MSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR2_LSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR2_MASK         0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR2_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR2_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR2_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR2_MSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR2_LSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR2_MASK          0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR2_MSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR2_LSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR1_MSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR1_LSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR1_MASK           0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR1_MSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR1_LSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR1_MASK         0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR1_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR1_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR1_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR1_MSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR1_LSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR1_MASK          0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR1_MSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR1_LSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR0_MSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR0_LSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR0_MASK           0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_NULL_QUEUE_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR0_MSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR0_LSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR0_MASK         0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR0_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR0_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QUEUE_PAUSED_USR0_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR0_MSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR0_LSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR0_MASK          0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_QMGR_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR0_MSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR0_LSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_13_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_13_ADDRESS                        0x0002b8
#define HWSCH_PAUSE_REASON_SCH_CMD_13_HW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_13_SW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_13_RSTMASK                        0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_13_RESET                          0x00000000

// 0x02bc (HWSCH_PAUSE_REASON_SCH_CMD_14)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_SCH_CMD_ILLEGAL_STATE_MSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_14_SCH_CMD_ILLEGAL_STATE_LSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_14_SCH_CMD_ILLEGAL_STATE_MASK     0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_14_SCH_CMD_ILLEGAL_STATE_GET(x)   (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_SCH_CMD_ILLEGAL_STATE_SET(x)   (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_SCH_CMD_ILLEGAL_STATE_RESET    0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_RESERVED_0_MSB                 30
#define HWSCH_PAUSE_REASON_SCH_CMD_14_RESERVED_0_LSB                 13
#define HWSCH_PAUSE_REASON_SCH_CMD_14_RESERVED_0_MASK                0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_14_RESERVED_0_GET(x)              (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_RESERVED_0_SET(x)              (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_RESERVED_0_RESET               0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_FES_SETUP_ABORT_MSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_14_FES_SETUP_ABORT_LSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_14_FES_SETUP_ABORT_MASK           0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_14_FES_SETUP_ABORT_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_FES_SETUP_ABORT_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_FES_SETUP_ABORT_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR2_MSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR2_LSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR2_MASK           0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR2_MSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR2_LSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR2_MASK         0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR2_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR2_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR2_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR2_MSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR2_LSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR2_MASK          0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR2_MSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR2_LSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR1_MSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR1_LSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR1_MASK           0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR1_MSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR1_LSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR1_MASK         0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR1_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR1_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR1_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR1_MSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR1_LSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR1_MASK          0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR1_MSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR1_LSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR0_MSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR0_LSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR0_MASK           0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_NULL_QUEUE_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR0_MSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR0_LSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR0_MASK         0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR0_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR0_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QUEUE_PAUSED_USR0_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR0_MSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR0_LSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR0_MASK          0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_QMGR_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR0_MSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR0_LSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_14_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_14_ADDRESS                        0x0002bc
#define HWSCH_PAUSE_REASON_SCH_CMD_14_HW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_14_SW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_14_RSTMASK                        0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_14_RESET                          0x00000000

// 0x02c0 (HWSCH_PAUSE_REASON_SCH_CMD_15)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_SCH_CMD_ILLEGAL_STATE_MSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_15_SCH_CMD_ILLEGAL_STATE_LSB      31
#define HWSCH_PAUSE_REASON_SCH_CMD_15_SCH_CMD_ILLEGAL_STATE_MASK     0x80000000
#define HWSCH_PAUSE_REASON_SCH_CMD_15_SCH_CMD_ILLEGAL_STATE_GET(x)   (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_SCH_CMD_ILLEGAL_STATE_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_SCH_CMD_ILLEGAL_STATE_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_SCH_CMD_ILLEGAL_STATE_SET(x)   (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_SCH_CMD_ILLEGAL_STATE_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_SCH_CMD_ILLEGAL_STATE_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_SCH_CMD_ILLEGAL_STATE_RESET    0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_RESERVED_0_MSB                 30
#define HWSCH_PAUSE_REASON_SCH_CMD_15_RESERVED_0_LSB                 13
#define HWSCH_PAUSE_REASON_SCH_CMD_15_RESERVED_0_MASK                0x7fffe000
#define HWSCH_PAUSE_REASON_SCH_CMD_15_RESERVED_0_GET(x)              (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_RESERVED_0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_RESERVED_0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_RESERVED_0_SET(x)              (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_RESERVED_0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_RESERVED_0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_RESERVED_0_RESET               0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_FES_SETUP_ABORT_MSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_15_FES_SETUP_ABORT_LSB            12
#define HWSCH_PAUSE_REASON_SCH_CMD_15_FES_SETUP_ABORT_MASK           0x00001000
#define HWSCH_PAUSE_REASON_SCH_CMD_15_FES_SETUP_ABORT_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_FES_SETUP_ABORT_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_FES_SETUP_ABORT_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_FES_SETUP_ABORT_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_FES_SETUP_ABORT_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_FES_SETUP_ABORT_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_FES_SETUP_ABORT_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR2_MSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR2_LSB            11
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR2_MASK           0x00000800
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR2_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR2_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR2_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR2_MSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR2_LSB          10
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR2_MASK         0x00000400
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR2_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR2_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR2_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR2_MSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR2_LSB           9
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR2_MASK          0x00000200
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR2_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR2_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR2_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR2_MSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR2_LSB 8
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR2_MASK 0x00000100
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR2_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR2_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR2_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR2_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR2_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR2_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR2_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR1_MSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR1_LSB            7
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR1_MASK           0x00000080
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR1_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR1_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR1_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR1_MSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR1_LSB          6
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR1_MASK         0x00000040
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR1_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR1_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR1_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR1_MSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR1_LSB           5
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR1_MASK          0x00000020
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR1_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR1_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR1_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR1_MSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR1_LSB 4
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR1_MASK 0x00000010
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR1_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR1_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR1_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR1_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR1_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR1_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR1_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR0_MSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR0_LSB            3
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR0_MASK           0x00000008
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR0_GET(x)         (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR0_SET(x)         (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_NULL_QUEUE_USR0_RESET          0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR0_MSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR0_LSB          2
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR0_MASK         0x00000004
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR0_GET(x)       (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR0_SET(x)       (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QUEUE_PAUSED_USR0_RESET        0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR0_MSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR0_LSB           1
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR0_MASK          0x00000002
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR0_GET(x)        (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR0_SET(x)        (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_QMGR_PAUSED_USR0_RESET         0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR0_MSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR0_LSB 0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR0_MASK 0x00000001
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR0_GET(x) (((x) & HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR0_MASK) >> HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR0_LSB)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR0_SET(x) (((0x0 | (x)) << HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR0_LSB) & HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR0_MASK)
#define HWSCH_PAUSE_REASON_SCH_CMD_15_INVALID_QID_REQUESTED_USR0_RESET 0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_ADDRESS                        0x0002c0
#define HWSCH_PAUSE_REASON_SCH_CMD_15_HW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_15_SW_MASK                        0xffffffff
#define HWSCH_PAUSE_REASON_SCH_CMD_15_RSTMASK                        0x00000000
#define HWSCH_PAUSE_REASON_SCH_CMD_15_RESET                          0x00000000


#endif /* _MAC_HWSCH_REG_H_ */
